Elastic Buffer Overflow Underflow Detection
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Solution Overview
Problem
Existing elastic buffer systems face challenges in accurately detecting overflow and underflow states when dealing with asynchronous data transfer between digital circuits operating on different clock signals, particularly due to metastable states caused by unknown phase relationships between write and read clock signals.
Innovation Solution
The proposed elastic buffer system incorporates ring counters and AND/OR circuits to synchronize clock signals and detect overflow and underflow states, using a decode circuit to differentiate between these states by analyzing the outputs from the ring counters and temporary storage circuits, thereby eliminating the influence of metastable bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a comparison circuit is used to detect overflow and underflow states in an elastic buffer, then the detection function is provided, but the circuit complexity increases and metastable states cause detection errors
Solution Approach 1:
The patent divides the detection function into two separate detection circuits: one for detecting overflow states and another for detecting underflow states. Each detection circuit independently monitors its specific condition, avoiding the complexity and metastable issues of a single comparison circuit that would need to handle both conditions simultaneously. This segmentation allows for simpler, more reliable detection of each state separately.
2Adaptability or versatility
If write and read operations are performed asynchronously with different clock signals, then data transfer flexibility is improved, but phase differences cause pointer coincidence and data loss
Solution Approach 1:
The patent implements preliminary detection of overflow and underflow conditions before they actually occur. The detection circuits monitor the write and read pointers continuously and generate warning signals when the buffer approaches critical states, allowing the system to take preventive actions (such as pausing data transfer) before pointer coincidence and data loss occur. This proactive approach maintains data integrity while preserving asynchronous transfer flexibility.
3Reliability
If the buffer storage capacity is increased to prevent overflow, then data loss is reduced, but the time required to transfer data increases
Solution Approach 1:
The patent employs feedback mechanisms through the detection circuits that continuously monitor buffer status and provide real-time information about approaching overflow or underflow conditions. This feedback allows the system to dynamically adjust data transfer rates or pause operations when critical thresholds are approached, preventing data loss without requiring a large buffer capacity. The feedback loop enables efficient buffer utilization while maintaining data integrity.
Data Source
AI summary
An output of a first ring counter is held in a first storage circuit. Outputs of a second ring counter and the first storage circuit are input to a first AND circuit group. An output of a third ring counter and an output of the first storage circuit are input to a second AND circuit group. Outputs of the first AND circuit group are input to a first OR circuit. Outputs of the second AND circuit group are input to a second OR circuit. An output of the first OR circuit is stored in a second storage circuit. An output of the second OR circuit is stored in a third storage circuit. Outputs of the first and second OR circuits and outputs of the second and third storage circuits are supplied to a decode circuit, and are decoded to output an overflow signal and an underflow signal.