Elastic ECC Mapping for Multi-Bit Error Correction
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Solution Overview
Problem
Modern servers face challenges in maintaining high Reliability, Availability, and Serviceability (RAS) due to increasing memory capacity and decreasing operating voltages in DRAM devices, leading to multi-bit soft errors that standard SECDED ECC is unable to effectively correct, and existing error correction techniques either fail to provide sufficient protection or incur significant memory capacity overhead.
Innovation Solution
A system utilizing an ECC mapping table with multiple error correction modes, including cyclic error correcting codes capable of 4-bit to 6-bit error correction and 5-bit to 7-bit error detection, dynamically selects the appropriate ECC mode based on memory address ranges and soft error intensities, allowing for flexible error correction without reducing memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard SECDED ECC is used to protect DRAM devices, then single-bit errors can be corrected, but multi-bit errors caused by dense packing and low voltage cannot be effectively corrected
Solution Approach 1:
The patent implements dynamic ECC mode switching that adapts the error correction strength based on the error intensity detected in different memory address ranges. The system transitions from standard SECDED to stronger cyclic ECC modes (capable of correcting 4-6 bit errors) when multi-bit errors are detected, providing adaptability to varying error conditions without always using the strongest (and most resource-intensive) correction mode.
Solution Approach 2:
The system changes the ECC parameter (error correction strength) based on the detected error pattern. When multi-bit errors are detected in a memory region, the system switches to a stronger ECC mode with higher correction capability. This parameter change allows the system to effectively handle multi-bit errors while avoiding the overhead of always using strong ECC modes.
2Quantity of substance
If memory capacity is increased by densely packing DRAM devices, then server memory capacity requirements are met, but the percentage of multi-bit errors increases
Solution Approach 1:
The patent applies different ECC protection levels to different local regions of memory based on their error characteristics. The memory space is divided into address ranges, and each range can be assigned a different ECC mode strength according to the error intensity observed in that region. This local differentiation allows strong protection where needed while maintaining efficiency in regions with lower error rates.
Solution Approach 2:
The system dynamically adjusts the ECC protection level for different memory regions based on observed error patterns. When multi-bit errors are detected in a particular address range, the system activates stronger cyclic ECC modes for that region, while other regions continue to use standard SECDED. This dynamic adaptation allows the system to handle increased error rates from dense packing without sacrificing overall memory capacity.
3Use of energy by moving object
If operating voltage is decreased to enable DDR evolution, then power consumption is reduced, but noise margin is lowered causing increased susceptibility to multi-bit soft errors
Solution Approach 1:
The system compensates for the reduced noise margin at lower voltages by dynamically changing the ECC parameter (correction strength) based on the actual error conditions observed. When multi-bit errors occur despite low-voltage operation, the system switches to stronger cyclic ECC modes that can correct 4-6 bit errors, effectively compensating for the increased susceptibility caused by voltage reduction.
Solution Approach 2:
The system uses feedback from error detection to adjust the ECC protection level. When soft errors are detected in low-voltage operation, the system responds by activating stronger error correction modes for affected memory regions. This feedback mechanism allows the system to maintain reliability despite operating at lower voltages with reduced noise margins.
4Reliability
If remapping or re-organization of bits is used to correct errors, then clustered soft errors can be corrected, but the technique is not effective when soft errors are uniformly distributed
Solution Approach 1:
The system dynamically selects the appropriate error correction approach based on the error pattern detected. When errors are clustered in specific address ranges, the system can apply remapping techniques to those regions. When errors are uniformly distributed, the system switches to stronger cyclic ECC modes that provide comprehensive protection across all memory regions regardless of error distribution pattern.
Solution Approach 2:
The patent applies different correction strategies to different memory regions based on local error characteristics. For regions with clustered errors, remapping or re-organization can be applied locally. For regions with uniformly distributed errors, stronger ECC modes are applied. This local differentiation based on error patterns allows the system to effectively handle both types of error distributions.
5Reliability
If full or partial memory mirroring is used to correct multi-bit errors, then robust error correction is achieved, but effective memory capacity is reduced by half
Solution Approach 1:
Instead of mirror-entire memory, the patent applies strong cyclic ECC protection only to specific address ranges where multi-bit errors are detected. This localized application of strong error correction maintains robust protection for affected regions while preserving the capacity of the entire memory system, avoiding the 50% capacity loss associated with full mirroring.
Solution Approach 2:
The system applies partial mirroring in the sense that strong ECC protection is applied only to the extent necessary - specifically to address ranges where multi-bit errors are observed. Rather than implementing full memory mirroring, the system uses partial strong protection where needed, achieving robust error correction for critical regions without sacrificing half the memory capacity.
Data Source
AI summary
A system is provided for performing error correction in memory. During operation, the system can receive a memory access request from a host processor. The system can then compare a memory address specified in the memory access request with a set of entries in an error correction code (ECC) mapping table. In response to the system determining that the memory address corresponds to at least one entry in the ECC mapping table, the system may determine, based on value in the counter field, whether the memory address belongs to a first portion or a second portion of the address range specified in the ECC mapping table entry. The system can then select a current ECC mode when the memory address belongs to the first portion; and select a previous ECC mode when the memory address belongs to the second portion. The system may then process the memory access request based on the selected ECC mode.