Elastic Gear FIFO Buffer With Frequency Monitor
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Solution Overview
Problem
Conventional asynchronous gear FIFO buffer designs are area-inefficient and introduce unwanted data latency when used between computing subsystems with different clock domains and data widths, as they require additional synchronous converters and are constrained to the same input and output data width.
Innovation Solution
An elastic gear FIFO buffer design that includes a frequency monitor unit and an elastic reset module, allowing for different read and write clock frequencies and data widths, with a simple addressing logic that optimizes FIFO depth and minimizes latency by dynamically adjusting pointer movement based on clock frequency differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional asynchronous gear FIFO buffer design is used, then data transfer between different clock domains is enabled, but circuit area increases and data latency is introduced
Solution Approach 1:
The patent combines the asynchronous FIFO buffer and synchronous gear FIFO buffer into a single integrated elastic gear FIFO buffer design. The write pointer and read pointer directly address memory locations without requiring separate conversion stages, merging the functions of asynchronous buffering and synchronous data width conversion into one unified structure that reduces overall circuit area.
Solution Approach 2:
The elastic gear FIFO buffer design serves multiple functions simultaneously: it acts as an asynchronous FIFO buffer for different clock domains, a data width converter for different port widths, and a latency optimization device. This multi-functionality eliminates the need for separate dedicated converters, reducing the total circuit area required.
2Adaptability or versatility
If conventional asynchronous gear FIFO buffer design is used, then data transfer between different clock domains is enabled, but data latency increases
Solution Approach 1:
The write pointer and read pointer are pre-calculated to directly address the correct memory locations based on the elastic gear ratio. This preliminary addressing calculation eliminates the need for intermediate pointer conversions and synchronization delays, allowing data to be written and read with minimal latency while still supporting different clock domains.
3Adaptability or versatility
If conventional asynchronous gear FIFO buffer design is used, then data width conversion is enabled, but additional synchronous converter is required
Solution Approach 1:
The patent merges the data width conversion function directly into the FIFO buffer structure. The write pointer and read pointer are designed to natively support different data widths (M bits for write, N bits for read) without requiring an external synchronous gear FIFO buffer converter, thereby simplifying the overall device architecture.
4Device complexity
If conventional asynchronous gear FIFO buffer design is used, then same input and output data width is constrained, but design simplicity is maintained
Solution Approach 1:
The patent implements dynamic pointer addressing where the write pointer operates with M-bit width and the read pointer operates with N-bit width, allowing the system to adapt to different data width requirements. This dynamic configuration enables the FIFO buffer to handle variable data widths between input and output ports while maintaining a relatively simple core design structure.
Data Source
AI summary
An elastic gear First-In-First-Out (FIFO) buffer architecture is disclosed. The proposed elastic gear FIFO buffer uses a frequency monitor unit to control clock frequency compensation. By using an independent frequency monitor unit, the data latency and FIFO buffer size are best optimized. An elastic gear FIFO could be utilized in applications where clock compensation and asynchronous data width conversion are desired or required.