Elastic Persistent Memory Regions Using DRAM-NAND Caching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies, such as NVDIMMs, are expensive and have limitations that prevent them from scaling to modern system architectures, and conventional approaches restrict the size of persistent memory regions (PMRs) to a small amount, making them inadequate for applications requiring larger memory sizes.
Innovation Solution
A memory sub-system that enables elastic PMRs by allocating a portion of the PMR to volatile memory devices, such as DRAM, and non-volatile memory devices, like NAND, with a caching mechanism to optimize access latency and hit rate, allowing larger memory regions to be exposed to the host system without increasing physical footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional approaches are used to allocate memory buffer resources, then host system transparency is maintained, but the size of persistent memory regions is restricted to a small amount
Solution Approach 1:
The persistent memory region is segmented into multiple buffer regions (first buffer region, second buffer region, third buffer region) that can be independently allocated and managed. This segmentation allows the system to expose a larger total memory region to the host while maintaining granular control over each segment, resolving the contradiction between memory size and allocation complexity.
Solution Approach 2:
The buffer allocation is made dynamic through runtime adjustments. The system can dynamically allocate buffers to different host functions based on demand, and the host can modify buffer allocations during operation. This dynamic approach enables the system to provide large memory regions while adapting complexity to actual usage patterns rather than requiring complex static allocation.
2Reliability
If NVDIMMs are used to provide persistent memory, then persistence is ensured, but cost increases and scalability is limited
Solution Approach 1:
The system merges volatile memory (DRAM buffers) with non-volatile memory (NAND storage) into a unified persistent memory region. The volatile buffers provide fast access for active data while the non-volatile storage ensures persistence. This combination allows the system to provide large memory capacity with persistence guarantees without the high cost of pure NVDIMM implementations.
Solution Approach 2:
The controller acts as an intermediary between the host, volatile buffers, and non-volatile storage. It manages the caching hierarchy, determining which data resides in volatile buffers versus non-volatile storage, and handles persistence operations. This intermediary approach enables large scalable memory capacity with persistence while keeping costs lower than direct-attached NVDIMMs.
3Quantity of substance
If larger memory regions are exposed to the host, then memory capacity increases, but physical footprint and cost increase
Solution Approach 1:
The system implements a nested memory hierarchy where volatile DRAM buffers are nested within the larger persistent memory region, which in turn is nested within the non-volatile NAND storage. This nesting allows the system to expose a large memory region to the host while using a small fraction of that space for expensive volatile memory, thereby reducing physical footprint and cost.
Solution Approach 2:
The system changes the physical state parameters of memory allocation by using high-speed volatile memory for frequently accessed data and transitioning less frequently accessed data to non-volatile storage. This parameter change in memory state (volatile vs. non-volatile) allows large exposed memory regions while minimizing the physical footprint of expensive volatile memory components.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a nonvolatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.