Conductive Via With Elastic Member for Crack-Resistant Wafer Bonding

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Solution Overview

Problem

The semiconductor industry faces challenges in integrating smaller components with increased complexity, which can lead to manufacturing difficulties such as crack formation and damage during wafer-to-wafer bonding processes.

Innovation Solution

Incorporating an elastic member within a conductive via of a semiconductor structure, which can absorb bonding forces and thermal stress, thereby minimizing the risk of cracks and damage during the bonding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer-to-wafer bonding process is performed with smaller components and increased integration density, then manufacturing precision and integration density are improved, but crack formation and structural damage occur due to bonding forces and thermal stress

Engineering Contradiction:
Improveintegration densityVSAvoidcrack formation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

An elastic member is disposed within the conductive via before the wafer-to-wafer bonding process to absorb bonding forces and thermal stress that will be generated during bonding, preventing crack formation and structural damage in advance

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The elastic member acts as an intermediary element between the conductive via and the surrounding substrate/passivation layer, absorbing mechanical stress and thermal expansion forces to protect the bonded structure from damage

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conductive via is made taller to accommodate elastic member, then stress absorption capability is improved, but via complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvestress absorptionVSAvoidvia structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The elastic member is nested within the conductive via, with the dielectric liner surrounding both the via and the elastic member, creating a compact multi-layer structure that maximizes stress absorption within limited space

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The elastic member effectively absorbs bonding forces and thermal stress, reducing the likelihood of cracks and damage in the bonded semiconductor structure, thus enhancing manufacturing reliability.

Implementation Method 1

an elastic member disposed within the conductive via

Methodology Applied
Scientific EffectElasticity: Elasticity

Implementation Method 2

a dielectric liner between the conductive via and the wafer, and between the conductive via and the passivation layer

Methodology Applied
Scientific EffectDielectric insulation: Dielectric

Data Source

PatentUS12272620B2Semiconductor structure having elastic member within via
Publication Date: 2025.04.08 NAN YA TECH
  • US12272620B2 patent drawing
  • US12272620B2 patent drawing
  • US12272620B2 patent drawing

AI summary

The present application provides a semiconductor structure having an elastic member within a via. The semiconductor structure includes a wafer including a substrate, a dielectric layer under the substrate, and a conductive pad surrounded by the dielectric layer; a passivation layer disposed over the substrate; a conductive via extending from the conductive pad through the substrate and the passivation layer and partially through the dielectric layer; and an elastic member disposed within the conductive via.