Electrical Alignment Marks for Wafer Stack Precision
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Solution Overview
Problem
Traditional optical alignment marks in semiconductor lithography are inadequate due to limited space on shrinking wafer surfaces and are ineffective for opaque layers, leading to alignment accuracy issues and reduced production yield.
Innovation Solution
A novel electrical alignment mark set comprising top, bottom, and optional middle marks with pads and monitoring vias, allowing for electrical connection and alignment optimization, even in non-transparent substrates, using Through-Silicon Via technology to create a conductive path for precise alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional optical alignment marks are used, then alignment detection can be performed, but the mark size must be large enough which consumes valuable wafer surface area
Solution Approach 1:
The patent replaces the optical detection system with an electrical detection system. Instead of using optical alignment marks that require large surface area for light detection, the invention uses electrical alignment marks with conductive pads and vias that can be detected through electrical measurements, enabling smaller mark sizes while maintaining alignment detection precision.
Solution Approach 2:
The patent changes the detection parameter from optical properties (light reflection, absorption) to electrical properties (conductivity, resistance). By transforming the alignment mark detection from an optical measurement to an electrical measurement, the system can use much smaller conductive features while achieving the same or better detection precision.
2Measurement precision
If optical alignment marks are used, then alignment can be detected, but they are ineffective for opaque layers
Solution Approach 1:
The patent replaces optical detection with electrical detection to enable alignment mark functionality on opaque substrates. Electrical signals can penetrate or be conducted through opaque materials via conductive paths, allowing the same electrical alignment mark system to work on both transparent and opaque layers without modification.
Solution Approach 2:
The electrical alignment mark system provides universal applicability across different substrate types (transparent and opaque) and layer configurations. The conductive pad and via structure can function as alignment marks regardless of the optical properties of the underlying material, making the system versatile for various semiconductor manufacturing scenarios.
3Adaptability or versatility
If multiple layers are stacked, then more functionality is achieved, but optical alignment marks become too weak to be detected
Solution Approach 1:
The patent replaces optical detection with electrical detection to overcome the signal weakness problem in multi-layer stacks. Electrical signals through conductive vias can be measured with high precision even through multiple layers, maintaining detection strength regardless of the number of stacked layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise alignment of wafer stacks with reduced mark size, effective alignment in multiple layers, and improved yield by using electrical signals instead of optical detection, suitable for opaque substrates, and facilitates optimal electrical readings for perfect alignment.
Implementation Method 1
at least one monitoring via which is disposed in the top wafer and electrically connected to the first pad and to the second pad
Data Source
AI summary
A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack.