Electrical Distance-Based Remapping for Memory Cell Wear
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Solution Overview
Problem
Threshold-type memory devices experience uneven wear and response due to differences in electrical properties at various intersections of wordlines and bitlines, leading to premature degradation of memory cells closer to drivers.
Innovation Solution
The memory device employs remapping circuitry to relocate addresses of memory cells susceptible to high driving voltages based on their electrical distance from drivers, remapping them to locations farther away that are less prone to wear, using lookup tables to manage this process transparently to host devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are organized in a cross-point array with wordlines and bitlines, then memory access capability is improved, but uneven wear and premature degradation occur in memory cells closer to drivers
Solution Approach 1:
The patent applies preliminary action by proactively remapping memory cells that are susceptible to high driving voltages before they actually degrade. The system identifies memory cells with electrical distance below a threshold and preemptively relocates their data to safer locations, preventing wear before it occurs rather than waiting for degradation to happen
Solution Approach 2:
The patent introduces an intermediary remapping circuit that acts as a mediator between the host device and the memory array. This intermediary layer transparently handles the complexity of uneven wear by automatically remapping addresses without requiring host device intervention, thus protecting memory cells while maintaining normal operation
2Duration of action of stationary object
If remapping circuitry is added to relocate memory cell addresses, then memory cell lifespan is extended, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory device to automatically monitor and remap its own memory cell addresses without external intervention. The remapping circuitry continuously evaluates electrical distance metrics and autonomously relocates data from vulnerable cells to safer locations, allowing the system to self-correct wear issues without host device involvement
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting memory cell address mappings based on electrical distance parameters. The system calculates electrical distance from drivers to each memory cell and remaps addresses when this parameter falls below a threshold, adapting the memory organization to compensate for physical wear patterns
3Speed
If memory cells are located closer to drivers for faster access, then access speed is improved, but wear and response uniformity deteriorate
Solution Approach 1:
The patent applies local quality by treating different regions of the memory array differently based on their electrical characteristics. Memory cells closer to drivers are identified as having different wear susceptibility and are proactively remapped to locations with more uniform electrical properties, creating localized quality adjustments that compensate for position-dependent wear patterns
Data Source
AI summary
Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured to transmit a corresponding signal to respective memory cells of the multiple memory cells. Remapping circuitry is configured to remap a near memory cell of the multiple memory cells to a far memory cell of the multiple memory cells. The near memory cell is relatively nearer to a respective driver of the multiple drivers than the far memory cell is to a respective driver of the multiple drivers.