Electro-optic Device Wiring Segmentation to Reduce Intersections
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Solution Overview
Problem
Existing electro-optic devices with multiple IC chips face increased manufacturing costs and short-circuit risks due to the complex intersection of electric supply lines, which complicates the wiring patterns and signal transmission.
Innovation Solution
The electro-optic device design reduces the number of intersections between wiring patterns by using a configuration where IC chips have symmetrically arranged power and signal terminals, with power and signal trunk lines that indirectly supply potentials, allowing for simplified wiring and reduced intersections between power and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If common electric supply lines are used to supply potentials to multiple IC chips, then the wiring structure becomes complex with multiple intersections, but this increases manufacturing cost and short-circuit risk
Solution Approach 1:
The patent divides the power supply system into separate segments for different IC chips. Each IC chip has its own dedicated power supply lines (e.g., first power supply line 65 for potential V1, second power supply line 66 for potential V2) that do not intersect with each other. This segmentation eliminates the need for complex intersecting wiring patterns while maintaining independent power supply to each chip, thereby reducing manufacturing cost and short-circuit risk.
2Reliability
If common electric supply lines are used to supply potentials to multiple IC chips, then the wiring structure becomes complex with multiple intersections, but this increases short-circuit risk
Solution Approach 1:
The patent segments the power supply wiring into independent paths for each IC chip. The first power supply line 65 supplies potential V1 to first power terminals RAn without intersecting with the second power supply line 66 that supplies potential V2 to second power terminals RBn. This physical separation of power supply paths eliminates intersection points where short-circuits could occur, thereby improving reliability while avoiding complex wiring structures.
3Ease of manufacture
If multiple intersections of electric supply lines are used, then power can be supplied to all IC chips, but this increases manufacturing cost
Solution Approach 1:
The patent implements segmented power supply lines where the first power supply line 65 and second power supply line 66 run in parallel without intersecting. This segmentation allows efficient use of substrate area by eliminating redundant wiring paths and intersection regions, thereby reducing manufacturing cost while maintaining complete power supply coverage to all IC chips.
Data Source
AI summary
An electro-optic device includes a substrate on which a plurality of electro-optic elements are configured, a plurality of IC chips that drive the electro-optic elements, and a plurality of wiring patterns. Each of the IC chips includes a first power terminal and a second power terminal connected to each other in the IC chip, a third power terminal sandwiching the first power terminal with the second power terminal and placed on a first side opposite to the second power terminal, and a fourth power terminal sandwiching the second power terminal with the first power terminal and placed on a second side opposite to the first power terminal. The wiring patterns include a first power trunk line connecting the second power terminal in a first IC chip among from the IC chips and the first power terminal in a second IC chip placed on the second side of the first IC chip, a second power trunk line connecting the fourth power terminal in the first IC chip and the third power terminal in the second IC chip, a first electric supply line that supplies a first potential for driving the electro-optic elements from a power supply circuit to the first power terminal in the first IC chip, and a second electric supply line that supplies a second potential for driving the electro-optic elements from the power supply circuit to the third power terminal in the first IC chip.