Electro-Optical Circuit Stacking for Warpage and Heat Dissipation
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Solution Overview
Problem
Existing optical and electrical circuits packaged together face issues of warpage due to mechanical stresses and increased heat dissipation challenges as network speeds increase, degrading device performance and reliability.
Innovation Solution
A circuit design that includes a photonic integrated circuit stacked on an intermetal dielectric with an electronic integrated circuit embedded in an oxide layer, connected via through oxide vias, which improves mechanical stability and thermal conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If optical circuits are packaged with electrical circuits to accommodate increasing network speeds, then network speed capability is improved, but mechanical stress-induced warpage increases
Solution Approach 1:
The patent introduces an intermetal dielectric layer as an intermediary between the photonic integrated circuit and the oxide layer containing electronic integrated circuits. This intermediate layer acts as a mechanical buffer that absorbs and distributes thermal expansion stresses, preventing direct stress transmission that would cause warpage. The intermetal dielectric serves as a mediator that enables close packaging for high-speed performance while maintaining mechanical stability through its stress-absorbing properties.
2Speed
If optical circuits are packaged with electrical circuits to accommodate increasing network speeds, then network speed capability is improved, but heat dissipation challenges increase
Solution Approach 1:
The patent segments the integrated circuit package into distinct functional layers: a photonic integrated circuit layer for optical signal processing, an intermetal dielectric layer for electrical isolation and stress management, and an oxide layer containing electronic integrated circuits for electrical processing. This segmentation allows each layer to be optimized for its specific function, including thermal management strategies tailored to photonic and electronic components, thereby addressing heat dissipation challenges in high-speed networks.
Solution Approach 2:
The intermetal dielectric layer serves as a thermal intermediary between the photonic and electronic integrated circuits. It provides a controlled thermal pathway that manages heat flow from both circuit types, preventing heat accumulation and facilitating dissipation to surrounding structures, thus addressing the heat dissipation challenges arising from close packaging.
3Stability of the object's composition
If electronic integrated circuit is embedded in oxide layer with through oxide vias, then mechanical stability is improved, but manufacturing complexity increases
Solution Approach 1:
The oxide layer in the patent serves multiple functions simultaneously: it provides mechanical support and stability for the embedded electronic integrated circuit, acts as an insulating layer, and contains through-oxide vias for electrical interconnections. The intermetal dielectric layer also performs multiple roles including electrical isolation, mechanical stress buffering, and thermal management. This multi-functionality reduces the need for additional separate components, thereby managing manufacturing complexity while achieving mechanical stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces warpage risk and enhances thermal management, maintaining operational temperatures and improving device reliability and performance.
Implementation Method 1
enhances thermal management, maintaining operational temperatures
Data Source
AI summary
The present disclosure relates to an opto-electrical circuit and a method of forming an opto-electrical circuit. According to an embodiment, a circuit includes a photonic integrated circuit, an intermetal dielectric, an oxide layer, and a first electronic integrated circuit. The intermetal dielectric is coupled to the photonic integrated circuit. The oxide layer is coupled to the intermetal dielectric such that the intermetal dielectric is positioned between the photonic integrated circuit and the oxide layer. The first electronic integrated circuit is positioned within the oxide layer and coupled to the intermetal dielectric. A through oxide via extends through the oxide layer to the intermetal dielectric.