Electro-optical Device Logical Operation Circuits Timing Adjustment

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Solution Overview

Problem

In electro-optical devices with increased data lines for higher definition, the demultiplexer system faces challenges in maintaining selection period efficiency and monitoring output signals from inspection circuits due to narrowed switch OFF periods.

Innovation Solution

The electro-optical device incorporates a first and second switch controlled by distinct signals, a sequential output circuit, and logical operation circuits to generate logical product and sum signals, facilitating signal distinction and improved timing adjustment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the number of data lines is increased to satisfy higher definition demand, then the definition quality is improved, but the selection period per data line is reduced

Engineering Contradiction:
Improvedefinition qualityVSAvoidselection period per data line
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent segments the data lines into multiple groups, with each group handled by a dedicated demultiplexer. This allows parallel processing of multiple data lines simultaneously, increasing the effective selection period for each group while maintaining support for a larger total number of data lines required for higher definition displays.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a group dimension in addition to the individual data line dimension. By organizing data lines into groups and using multiple demultiplexers, the system adds a hierarchical structure that allows more data lines to be managed without proportionally reducing the selection period for each group.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the period between switch ON periods is narrowed to maintain selection period efficiency, then the selection period efficiency is improved, but the ability to monitor output signals from inspection circuit is degraded

Engineering Contradiction:
Improveselection period efficiencyVSAvoidmonitoring output signal
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces an inspection circuit as an intermediary component that includes buffer circuits and level shifters. These intermediary elements are strategically placed to allow signal monitoring during the narrow OFF periods, acting as a bridge between the high-speed switching operation and the inspection requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The inspection circuit performs preliminary signal buffering and level shifting in advance, preparing signals for monitoring before the actual switching occurs. This preliminary action ensures that signals can be captured and analyzed even during the brief intervals when switches are OFF.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11367408B2Electro-optical device and electronic apparatus having two logical operation circuits
Publication Date: 2022.06.21 SEIKO EPSON CORP
  • US11367408B2 patent drawing
  • US11367408B2 patent drawing
  • US11367408B2 patent drawing

AI summary

An electro-optical device includes a first switch provided between an input node supplied with a data signal and a first data line, the first switch being configured to be turned ON or OFF by a first control signal, a second switch provided between the input node and a second data line, the second switch being configured to be turned ON or OFF by the second control signal, a sequential output circuit configured to output a first pulse, and a second pulse exclusive of the first pulse, logical operational first logical operation circuit configured to acquire a first logical product signal of the first control signal and the first pulse, and a second logical product signal of the second control signal and the second pulse, and a second logical operation circuit configured to generate a logical sum signal of the first logical product signal and the second logical product signal.