Electro-Optical Memory Package With Stacked PIC Access

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Solution Overview

Problem

Existing integrated circuits, particularly those for artificial intelligence and machine learning, face challenges in scaling data movement between processor ICs and memory ICs due to inadequate advancements in data transfer components, which cannot keep pace with the increasing demand for faster and more efficient data processing.

Innovation Solution

The implementation of electro-photonic circuit packages with stacked memory resources directly accessible by EIC dies, utilizing optical regions and photonic interfaces for direct data transfer, enabling efficient data access and communication between components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional electrical interconnects are used for data transfer between processor ICs and memory ICs, then the system can maintain simple electrical connections, but the data transfer speed and efficiency cannot keep pace with increasing processing demands

Engineering Contradiction:
Improvedata transfer speedVSAvoidinterconnect architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces traditional electrical interconnects with optical interconnects using photonic integrated circuits (PICs). Light-based communication substitutes for electrical signals, enabling faster data transfer between processor ICs and memory ICs while overcoming the bandwidth limitations of electrical interconnects.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements three-dimensional stacking architecture where processor ICs and memory ICs are vertically stacked with PICs positioned between them. This vertical arrangement in the third dimension enables direct optical coupling and reduces the physical distance for data transfer, significantly improving speed and efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If data transfer components are advanced to meet higher speeds, then data transfer efficiency improves, but the complexity of the interconnect architecture increases beyond current scaling capabilities

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidinterconnect architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges electrical and optical interconnect functions into a unified architecture. Electrical interconnects handle control signals and power, while optical interconnects handle high-bandwidth data transfer. This consolidation achieves high productivity without requiring completely separate complex systems.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Photonic integrated circuits serve as intermediary components between processor ICs and memory ICs. The PICs convert electrical signals to optical signals for high-speed data transfer and back to electrical signals for processing, enabling efficient data movement without direct electrical connections between distant ICs.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If optical interconnects are implemented for high-speed data transfer, then data movement efficiency increases, but the packaging and integration complexity increases

Engineering Contradiction:
Improvedata movement speedVSAvoidpackaging and integration difficulty
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

Photonic integrated circuits are pre-fabricated and tested as complete functional units before being integrated into the final stacked package. This preliminary preparation simplifies the packaging process by reducing on-site assembly complexity and ensuring optical alignment is established during PIC manufacturing rather than during final integration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a nested stacking architecture where PICs are positioned within the vertical stack between processor ICs and memory ICs. The optical components are nested within the package structure, with optical pathways routed through the vertical arrangement, enabling compact integration while maintaining high-speed data transfer capabilities.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances data transfer efficiency by allowing direct access to memory stacks via optical regions, facilitating faster and more robust communication within limited space constraints, thereby supporting the growing demand for data processing in integrated circuits.

Implementation Method 1

an optical portion stacked below the first die, the optical portion being configured to, in cooperation with the electrical portion, transform instructions from an optical signal to an electrical signal when receiving or transform instructions from an electrical signal to an optical signal when transmitting

Methodology Applied
Scientific EffectElectro-optic conversion: Electro-Optic Effects

Implementation Method 2

an optical region on a top surface of the second die, the optical region not intersecting with the first die, the optical region being configured to allow an optical signal to pass through to facilitate communication with another device

Methodology Applied
Scientific EffectOptical signal transmission: Light

Data Source

PatentUS20250370183A1Electro-optical memory circuit package
Publication Date: 2025.12.04 SICILY MERGER SUB II INC
  • US20250370183A1 patent drawing
  • US20250370183A1 patent drawing
  • US20250370183A1 patent drawing

AI summary

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing memory circuit packages having memory stacks positioned on top of electronic integrated (EIC) dies positioned over one or more PIC wafers. Techniques described herein also relate to forming overmolded memory circuit packages having optical interfaces which are optically accessible via optical window(s).