Electro-optical Device Multilayer Scanning Lines Optical Leakage

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Solution Overview

Problem

Existing electro-optical devices face challenges in achieving high resolution and suppressing optical leakage current due to difficulties in multilayering scanning lines and electrical coupling, while also effectively blocking light from entering semiconductor films.

Innovation Solution

The electro-optical device incorporates a substrate with a first scanning line and a second scanning line, both with light shielding properties, where the semiconductor film overlaps with the first scanning line, and the second scanning line is electrically coupled to the gate electrode and first scanning line, allowing for multilayered wiring and reduced optical leakage by strategically positioning the scanning lines and contact portions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If the semiconductor film is formed so as not to overlap with the scanning line in plan view, then optical leakage current is suppressed, but it becomes difficult to electrically couple the semiconductor film and the data line or pixel electrode

Engineering Contradiction:
Improveoptical leakage currentVSAvoidelectrical coupling
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. The semiconductor film is positioned in a lower layer while scanning lines are placed in upper layers, allowing vertical electrical coupling through contact holes while maintaining horizontal separation to block optical leakage. This dimensional transition enables both non-overlapping planar views for optical isolation and vertical connections for electrical coupling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested multi-layer structure where the semiconductor film is embedded in a lower layer and scanning lines are nested in upper layers. Contact holes penetrate through intermediate insulating layers to establish vertical electrical connections from the semiconductor film to upper-layer scanning lines, data lines, and pixel electrodes, creating a nested configuration that achieves both optical isolation and electrical connectivity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Loss of time

If wiring lines are made multilayered to reduce the resistance of the scanning line, then the time constant in the scanning line is reduced, but it becomes difficult to suppress optical leakage current into the semiconductor film

Engineering Contradiction:
Improvetime constantVSAvoidoptical leakage current
Core Design Contradiction:
Loss of timeVSObject-generated harmful factors

Solution Approach 1:

The patent resolves this contradiction by stacking scanning lines in multiple vertical layers rather than extending them in a single plane. This allows the scanning lines to achieve lower resistance through parallel multilayer paths while the vertical separation between layers prevents optical leakage. The semiconductor film remains in a lower layer with scanning lines positioned in upper layers, maintaining both low resistance and optical isolation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies different spatial configurations to different functional elements: the semiconductor film is localized in a lower layer to receive light, while scanning lines are localized in upper layers to provide light shielding. Contact holes are strategically positioned to provide localized electrical coupling points, creating local quality variations that simultaneously achieve low resistance scanning lines and optical leakage suppression.

Inventive Principle:
Principle #3Local quality

3Reliability

If the semiconductor film overlaps with the scanning line in plan view, then electrical coupling is facilitated, but optical leakage current increases

Engineering Contradiction:
Improveelectrical couplingVSAvoidoptical leakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent eliminates planar overlap between the semiconductor film and scanning lines by positioning them in different vertical layers. The semiconductor film resides in a lower layer while scanning lines are placed in upper layers, allowing electrical coupling through vertical contact holes without horizontal overlap. This vertical separation maintains electrical connectivity while preventing optical leakage paths.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces electrical resistance, minimizes optical leakage current, and enables high-resolution imaging while maintaining appropriate electrical coupling, thereby enhancing the performance of the electro-optical device.

Implementation Method 1

a first scanning line having a light shielding property and extending in a first direction in a layer between the substrate body and the pixel electrode

Methodology Applied
Scientific EffectLight shielding: Absorption (EM radiation)

Data Source

PatentUS11681187B2Electro-optical device and electronic device
Publication Date: 2023.06.20 SEIKO EPSON CORP
  • US11681187B2 patent drawing
  • US11681187B2 patent drawing
  • US11681187B2 patent drawing

AI summary

An electro-optical device including a first substrate and a transistor is provided. The first substrate includes a first scanning line having a light shielding property and extending in a first direction between a substrate body and a pixel electrode. The transistor includes a semiconductor film extending in the first direction to overlap with the first scanning line in a layer between the first scanning line and the pixel electrode. In a layer between a gate electrode and a pixel electrode, a second scanning line having a light shielding property extends in the first direction to overlap with the first scanning line in plan view. The second scanning line extends through a position spaced apart from a third contact portion that electrically couples the pixel electrode and the semiconductor film, and is electrically coupled to the gate electrode and the first scanning line.