Electro-optical Device Resolution Conversion via Clock Phase Control
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Solution Overview
Problem
Existing electro-optical devices face challenges in efficiently converting display resolution due to the complexity of generating modulated clock signals for low-resolution images on high-resolution displays, leading to increased costs and processing delays.
Innovation Solution
The method involves a driving configuration for electro-optical devices with separate scanning line driving circuits for odd and even scanning lines, using shift registers and output control circuits to generate logic signals and adjust pulse widths, allowing resolution change by phase adjustment of clock or enable signals, enabling easy resolution conversion between normal and low-resolution modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a modulated clock signal is used to display low-resolution images on a high-resolution display device, then resolution conversion is achieved, but the configuration becomes complicated due to the need for separate clock signal generation
Solution Approach 1:
The shift register is designed to accept either a normal clock signal or a modulated clock signal, making it multi-functional. By controlling the clock selection switch, the same shift register can operate in different modes (normal resolution or low-resolution display) without requiring separate dedicated circuits for each function, thus reducing overall device complexity while maintaining versatility
Solution Approach 2:
A clock selection switch is introduced as an intermediary component that selects between the normal clock signal and the modulated clock signal. This mediator allows the system to switch between different operating modes without direct complex interaction between the clock generation circuits and the shift register, simplifying the overall configuration by providing a clean interface for mode switching
2Adaptability or versatility
If a modulated clock signal with different duty ratio is generated from the reference clock signal, then low-resolution display is enabled, but processing delay increases
Solution Approach 1:
The modulated clock signal is generated in advance and stored in a buffer circuit before being needed for display. By preparing the modulated clock signal beforehand and making it available through the clock selection switch, the system avoids real-time conversion delays during actual display operation, thus reducing processing time loss while maintaining the capability to switch to low-resolution mode
3Adaptability or versatility
If separate modulated clock signal generation is implemented, then resolution conversion is achieved, but device cost increases
Solution Approach 1:
The shift register and associated circuits are designed to handle both normal and modulated clock signals, making them multi-functional. This universal design eliminates the need for separate dedicated low-resolution display circuits, reducing component count and manufacturing cost while maintaining the ability to perform resolution conversion when needed
Solution Approach 2:
The normal display circuit and low-resolution display circuit are merged into a single integrated system. By combining the clock signal input, shift register, and scanning line selection into one unified architecture that can accept different clock signal types, the patent reduces component proliferation and associated manufacturing costs while maintaining full resolution conversion capability
Data Source
AI summary
A method of driving an electro-optical device that has a plurality of pixel circuits provided so as to correspond to intersections of a plurality of scanning lines and a plurality of data lines, a first scanning line driving circuit for selecting odd-numbered scanning lines, a second scanning line driving circuit for selecting even-numbered scanning lines, and a data line driving circuit for supplying data signals corresponding to the selected scanning line through the data lines. The method includes, in a first mode, supplying enable signals having different phases to the first and second scanning line driving circuits, respectively, so as to alternately select odd-numbered and even-numbered scanning lines, and, in a second mode different from the first mode, supplying enable signals having the same phase to the first and second scanning line driving circuits, respectively, so as to simultaneously select adjacent odd-numbered and even-numbered scanning lines two by two.