Electro-Optical Device Scanning Line Width Reduction via Segmented Openings
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Solution Overview
Problem
In electro-optical devices, the configuration of a gate electrode and scanning line via openings in the semiconductor layer leads to a widened scanning line, reducing the pixel aperture ratio due to light shielding requirements, which affects the efficiency of light modulation and increases the risk of electrical interference between the gate electrode and semiconductor layer.
Innovation Solution
The electro-optical device incorporates a scanning line, a transistor with a semiconductor layer, a gate electrode with light shielding properties, and interlayer insulating layers with first and second openings, where the gate electrode is positioned opposite the scanning line, and capacitance elements with light shielding properties, allowing for efficient light blocking without widening the scanning line, thus maintaining a higher pixel aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate electrode and scanning line are electrically coupled via an opening provided in both sides of the semiconductor layer, then light shielding can be achieved by the gate electrode, but the width of the scanning line needs to be widened which reduces the pixel aperture ratio
Solution Approach 1:
The opening is divided into a first opening and a second opening provided in both sides of the semiconductor layer with the semiconductor layer interposed therebetween in plan view. The gate electrode is coupled to the scanning line via the first opening, while the capacitance element is coupled via the second opening. This segmentation allows separate optimization of light shielding and electrical coupling functions.
Solution Approach 2:
The gate electrode and capacitance electrode are positioned at different lateral positions relative to the semiconductor layer by providing openings on both sides. This spatial arrangement in the plan view dimension allows the gate electrode to provide light shielding while the capacitance element provides electrical coupling without requiring the scanning line to be widened.
2Reliability
If the semiconductor layer and opening are separated from each other to prevent electrical interference, then electrical stability is improved, but the width of the scanning line needs to be widened
Solution Approach 1:
The openings are segmented into first and second openings positioned at different lateral locations. The gate electrode is coupled via the first opening while the capacitance element is coupled via the second opening. This segmentation allows the semiconductor layer to be separated from the gate electrode opening to prevent electrical interference while maintaining proper electrical connections through the capacitance element.
Solution Approach 2:
The interlayer insulating layer acts as an intermediary between the semiconductor layer and the openings. The capacitance element is provided via the second opening through the interlayer insulating layer, mediating the electrical connection while maintaining proper spacing to prevent direct electrical interference between the gate electrode and semiconductor layer.
3Reliability
If the scanning line width is widened to accommodate the opening and separation requirements, then light shielding and electrical stability are achieved, but the pixel aperture ratio is reduced
Solution Approach 1:
The opening structure is segmented into first and second openings positioned at different lateral locations relative to the semiconductor layer. This segmentation allows the scanning line to be positioned optimally without requiring excessive width, as the gate electrode and capacitance element are distributed across different spatial locations rather than requiring a single wide opening.
Solution Approach 2:
The electrical coupling and light shielding functions are distributed across different lateral positions by providing openings on both sides of the semiconductor layer. This spatial distribution in the plan view dimension allows narrower scanning lines while maintaining all necessary functions, thereby preserving the pixel aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively blocks light from reaching the semiconductor layer, reduces off-leak current in the transistor, and allows for a narrower scanning line, enhancing light utilization efficiency and reducing electrical interference, thereby improving the device's performance and aperture ratio.
Implementation Method 1
a gate electrode having light shielding properties and disposed on a side of the semiconductor layer opposite from a side of the scanning line
Implementation Method 2
a capacitance element in which at least one of a first capacitance electrode and a second capacitance electrode has light shielding properties
Data Source
AI summary
In an electro-optical device, a first opening and a second opening are provided in an interlayer insulating layer provided in a layer between a transistor and a scanning line, with a semiconductor layer interposed between the first opening and the second opening in plan view. A portion of a gate electrode is provided inside the first opening, and the gate electrode is electrically connected to the scanning line via the first opening. The second opening does not overlap with the gate electrode, and a portion of a first capacitance electrode of a capacitance element is provided in the second opening, the first capacitance electrode having light shielding properties. Therefore, the width of the scanning line can be made narrower than in a case in which the gate electrode and the scanning line are electrically connected to each other via both the first opening and the second opening.