Electrode Terminal Bonding Layout for Flat Semiconductor Substrates
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Solution Overview
Problem
Existing semiconductor device manufacturing methods face challenges in achieving a flat and stable substrate during bonding, leading to warpage and misalignment issues which affect heat dissipation and manufacturing reliability.
Innovation Solution
The semiconductor device design incorporates a bonding process where the positive and negative electrode terminals have a thickness less than the circuit pattern layers, with bonding regions extending in the long-side direction, ensuring sufficient width to correct warpage and maintain a flat substrate, allowing for reliable bonding and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the bonding region thickness is reduced to improve heat dissipation, then heat dissipation performance is improved, but bonding strength and structural stability may deteriorate
Solution Approach 1:
The patent applies local quality by creating different thickness zones within the bonding region. The bonding region has a first thickness at the interface with the circuit pattern layer and a second thickness (greater than the first) at the free end, forming a tapered structure. This local variation in thickness allows the bonding interface to maintain strong adhesion while the overall structure provides improved heat dissipation pathways.
Solution Approach 2:
The patent employs composite material structure by combining the bonding region with different geometric profiles with the circuit pattern layer and insulating plate. The bonding region acts as a transition zone with optimized thickness distribution, creating a composite structure that simultaneously achieves strong bonding and efficient heat dissipation.
2Temperature
If the substrate is made thinner to improve heat dissipation, then heat dissipation is improved, but warpage and misalignment increase
Solution Approach 1:
The patent applies preliminary anti-action by designing the bonding region with a tapered thickness profile before final assembly. The greater thickness at the free end of the bonding region counteracts potential warpage forces, pre-establishing structural stability that prevents misalignment during bonding and operation.
Solution Approach 2:
The patent utilizes parameter changes by varying the thickness parameter of the bonding region along its length. The thickness transitions from a first value at the bonding interface to a second, greater value at the free end. This parameter variation optimizes both heat dissipation and structural stability, preventing substrate warpage while maintaining thermal performance.
3Reliability
If the bonding region length is increased to improve bonding reliability, then bonding reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bonding region into distinct zones based on thickness: a first zone at the bonding interface with smaller thickness and a second zone at the free end with greater thickness. This segmentation allows each zone to perform its specific function optimally while keeping the overall structure relatively simple.
Data Source
AI summary
A positive electrode circuit pattern layer and a negative electrode circuit pattern layer each have a terminal region extending in a long-side direction of a rectangular insulating plate. Thicknesses of a positive electrode bonding region of a positive electrode terminal and a negative electrode bonding region of a negative electrode terminal are respectively less than thicknesses of the terminal regions of the positive electrode circuit pattern layer and the negative electrode circuit pattern layer. The lengths in the long-side direction of the positive electrode bonding region of the positive electrode terminal and the negative electrode bonding region of the negative electrode terminal are respectively greater than or equal to half the lengths in the long-side direction of the terminal regions of the positive electrode circuit pattern layer and negative electrode circuit pattern layer.