Electrode Orientation for Bevel Edge Processing
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Solution Overview
Problem
In semiconductor manufacturing, accurately processing semiconductor wafers is hindered by the accumulation of undesired materials on the edge exclusion area, which interferes with central area processing and requires periodic cleaning to prevent material flaking, necessitating an apparatus that can uniformly remove these materials without damaging the central area.
Innovation Solution
The apparatus is designed to accurately align electrodes in a process chamber to define separate regions of process exclusion and performance, ensuring that etching is excluded from the central area and performed only on the edge environment, using a method that configures electrodes with reference surfaces and a fixture system to maintain parallel orientation and secure the upper electrode relative to the lower electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic cleaning is performed to remove undesired materials from the edge environ, then material flaking is prevented, but processing time is lost and productivity decreases
Solution Approach 1:
The patent applies preliminary action by performing edge environ cleaning before the accumulation of undesired materials becomes problematic. The system proactively removes materials during designated cleaning intervals before they can flake and contaminate device regions, preventing quality issues while minimizing disruption to overall processing throughput
Solution Approach 2:
The patent implements periodic action by scheduling cleaning operations at specific intervals during wafer processing. Rather than continuous cleaning, the system performs cleaning cycles at predetermined times when wafers are loaded or unloaded from the chamber, removing undesired materials periodically to prevent flaking while maintaining high productivity during active processing periods
2Area of stationary object
If etching is performed on the entire wafer surface, then complete coverage is achieved, but damage to the central area devices occurs
Solution Approach 1:
The patent applies local quality by creating spatially varying etching conditions across the wafer surface. The upper electrode is positioned closer to the edge environ than to the central area, generating higher plasma density and etching rate at the edges while maintaining lower intensity in the central region. This allows selective removal of undesired materials from the edge environ without damaging devices in the central area
Solution Approach 2:
The patent segments the wafer processing into distinct zones: the central area where devices are formed and protected from etching, and the edge environ where undesired materials are removed. The upper electrode configuration creates a non-uniform plasma distribution that naturally segments the etching action to specific regions, enabling simultaneous device protection and edge cleaning in a single processing step
Data Source
AI summary
Methods for orienting an upper electrode relative to a lower electrode are provided. The lower electrode is configured to have a desired existing orientation in a process chamber to define active and inactive process zones in the process chamber for processing a wafer. The method includes configuring each electrode with a reference surface, where a lower electrode reference surface is in the desired existing orientation and an upper electrode reference surface to be oriented parallel to the lower electrode reference surface. Then, temporarily holding the upper electrode reference surface oriented parallel to the lower electrode reference surface, and securing the upper electrode to a drive to mount the upper electrode reference surface parallel to the lower electrode reference surface. Other method configurations are also disclosed and illustrated.