Semiconductor Electrode Roughening for Void-Resistant Wiring Adhesion

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Solution Overview

Problem

The formation of voids between the electrode and the wiring layer in semiconductor devices inhibits effective conduction, necessitating improved adhesion of the wiring layer to the electrode.

Innovation Solution

A semiconductor device design featuring a first insulating layer with penetrating parts and grooves, a wiring layer with a base and plating layer, and a manufacturing method involving laser irradiation to form asperities on the electrode surface, enhancing the adhesion by increasing the surface roughness and contact area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a plating layer is formed to connect the wiring layer to the electrode, then electrical connectivity is achieved, but voids form between the electrode and wiring layer reducing adhesion

Engineering Contradiction:
Improveadhesion of wiring layer to electrodeVSAvoidvoid formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by forming a base layer on the electrode surface before forming the plating layer. This base layer is deposited in advance to ensure proper adhesion and prevent void formation during subsequent plating processes. The base layer serves as an intermediate layer that prepares the surface for optimal plating attachment.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by creating different surface regions on the electrode with different roughness characteristics. The connecting surface has a first region with greater surface roughness for enhanced adhesion and a second region with lesser surface roughness. This localized differentiation optimizes adhesion in critical areas while maintaining overall electrical connectivity.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the electrode surface is made smoother for better planarity, then manufacturing ease is improved, but adhesion of the wiring layer decreases

Engineering Contradiction:
Improveelectrode surface planarityVSAvoidwiring layer adhesion
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by creating different surface regions on the electrode with different roughness characteristics. The connecting surface has a first region with greater surface roughness for enhanced adhesion and a second region with lesser surface roughness. This localized differentiation optimizes adhesion in critical areas while maintaining overall electrical connectivity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies parameter changes by modifying the surface roughness parameter of the electrode in specific regions. The connecting surface includes a first region with greater surface roughness than a second region, creating optimal conditions for wiring layer adhesion while maintaining manufacturability through controlled surface variation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The improved adhesion of the wiring layer to the electrode enhances electrical connectivity and facilitates efficient mounting on a wiring board, reducing void formation and ensuring reliable conduction.

Implementation Method 1

a manufacturing method involving laser irradiation to form asperities on the electrode surface

Methodology Applied
Scientific EffectLaser irradiation: Laser

Data Source

PatentUS12431399B2Semiconductor device and method for manufacturing semiconductor device
Publication Date: 2025.09.30 ROHM CO LTD
  • US12431399B2 patent drawing
  • US12431399B2 patent drawing
  • US12431399B2 patent drawing

AI summary

A semiconductor device includes an insulating layer, a semiconductor element, a wiring layer and a sealing resin. The insulating layer includes obverse and reverse surfaces spaced apart in a thickness direction, and a penetrated part extending in the thickness direction. The semiconductor element, in contact with the obverse surface, includes an electrode corresponding to the penetrated part. The wiring layer includes connecting and main parts, where the connecting part is in the penetrated part and contacts the electrode, and the main part is connected to the connecting part on the reverse surface. The sealing resin, contacting the obverse surface, covers the semiconductor element. The electrode has a connecting surface facing the connecting part and including a first region exposed from the insulating layer through the penetrated part and a second region contacting the insulating layer. The first region has a greater surface roughness than the second region.