Electroless Barrier Layer for Post-Passivation Interconnects
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Solution Overview
Problem
Existing bump formation processes in semiconductor devices require physical vapor deposition and etching, leading to surface roughness and residue issues, which complicate the packaging process and reduce reliability.
Innovation Solution
A barrier layer formed through electroless plating replaces traditional under-bump metallization, eliminating the need for photolithography and etching, and is used to prevent copper diffusion, thereby simplifying the process and enhancing bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical vapor deposition and etching are used to form under-bump metallization, then metallization layers can be formed, but surface roughness increases and residues remain after wafer backside grinding
Solution Approach 1:
The patent extracts and eliminates the harmful etching step from the traditional UBM formation process. By using electroless plating alone to form the copper pad and barrier layer, the roughening etching step is completely removed, thereby eliminating surface roughness and residues while maintaining bonding reliability
Solution Approach 2:
The patent replaces the mechanical/physical etching process with a chemical electroless plating process. Instead of using physical vapor deposition followed by photolithography and etching, the invention uses electroless plating to directly form both the copper pad and barrier layer, substituting a chemical process for mechanical/physical processes that cause surface damage
2Manufacturing precision
If traditional photolithography and etching are used to define UBM area, then precise patterning can be achieved, but process complexity and manufacturing steps increase
Solution Approach 1:
The patent merges multiple process steps into a single electroless plating operation. The electroless plating process simultaneously forms both the copper pad and the barrier layer in one step, eliminating the need for separate PVD, photolithography, and etching steps, thereby reducing process complexity while maintaining patterning precision through the use of a sacrificial layer
Solution Approach 2:
The patent employs a preliminary sacrificial layer (such as photoresist) that is patterned beforehand to define the desired copper pad and barrier layer areas. This preliminary patterning action guides the subsequent electroless plating process, achieving precise patterning without requiring complex in-process lithography and etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces surface roughness, eliminates residue, and increases joint reliability by preventing copper diffusion, while simplifying the bump formation process and reducing costs.
Implementation Method 1
A barrier layer formed through electroless plating replaces traditional under-bump metallization
Data Source
AI summary
A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.