Electroless NiPdAu Plating for PCB High-Frequency Resistance
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Solution Overview
Problem
The thick nickel layer in existing electroless Ni/Au and Ni/Pd/Au surface treatment plated layers on printed circuit boards leads to increased electrical resistance due to the skin effect, especially at high frequencies, and prevents the reduction of space between patterns to 25 μm or less, causing electrical bridging issues.
Innovation Solution
An electroless surface treatment plated layer with reduced nickel, palladium, and gold coating thicknesses of 0.02 to 1 μm, 0.01 to 0.3 μm, and 0.01 to 0.5 μm respectively, containing 8 wt % or more phosphorus, is formed using an electroless plating method to minimize electrical resistance and prevent oxidation, allowing for improved wire bonding and reduced pattern spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick nickel layer (3 μm or more) is used in electroless Ni/Au or Ni/Pd/Au surface treatment, then the copper diffusion barrier performance is improved, but the electrical resistance increases due to the skin effect at high frequencies
Solution Approach 1:
The patent changes the thickness parameter of the nickel layer from the conventional 3 μm or more to a reduced thickness of 0.02 to 1 μm. This parameter change resolves the contradiction by eliminating the skin effect-induced electrical resistance while maintaining adequate copper diffusion barrier performance through the optimized thin nickel layer configuration
Solution Approach 2:
The patent applies different thickness specifications to different layers in the plated structure. The nickel layer is localized to a thin 0.02 to 1 μm thickness for electrical performance, while the overall plated layer structure (including Pd and Au layers) provides the necessary protective and barrier functions, creating local quality optimization throughout the layer stack
2Reliability
If a thick nickel layer (3 μm or more) is used in surface treatment, then the copper diffusion barrier performance is improved, but the space between patterns cannot be reduced to 25 μm or less due to abnormal nickel growth causing electrical bridging
Solution Approach 1:
The patent changes the nickel layer thickness parameter from 3 μm or more to 0.02 to 1 μm, which prevents abnormal nickel growth between patterns. This parameter change enables pattern spacing to be reduced to 25 μm or less while maintaining copper diffusion barrier performance through the optimized thin nickel layer
Solution Approach 2:
The patent applies a partial thickness of nickel (0.02 to 1 μm) that is sufficient for copper diffusion barrier function but insufficient to cause abnormal growth and electrical bridging between closely spaced patterns. This partial action approach provides just enough barrier protection without the excessive nickel deposition that would cause manufacturing defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced nickel layer thickness alleviates increased electrical resistance at high frequencies, enabling uniform current flow and preventing electrical bridging, while maintaining corrosion resistance and cost-effectiveness.
Implementation Method 1
an electroless surface treatment plated layer with reduced nickel, palladium, and gold coating thicknesses of 0.02 to 1 μm, 0.01 to 0.3 μm, and 0.01 to 0.5 μm respectively, containing 8 wt % or more phosphorus, is formed using an electroless plating method
Implementation Method 2
the thick nickel layer in existing electroless Ni/Au and Ni/Pd/Au surface treatment plated layers on printed circuit boards leads to increased electrical resistance due to the skin effect, especially at high frequencies
Implementation Method 3
containing 8 wt % or more phosphorus, is formed using an electroless plating method to minimize electrical resistance and prevent oxidation
Data Source
AI summary
An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 μm, 0.01 to 0.3 μm, and 0.01 to 0.5 μm, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 μm, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.