Electroless Plated Conductive Bump Structure Over Through Vias

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Solution Overview

Problem

In semiconductor manufacturing, the formation of conductive structures like micro-bumps or C4 structures requires complex multi-step processes involving intermediate under-bump metallization layers and photoresist patterning, which increases costs and lead times.

Innovation Solution

The use of electroless plating processes to directly form conductive layers over through vias and passivation layers without the need for intermediate under-bump metallization layers or patterned photoresist, allowing for self-aligned, tapered conductive structures with improved adhesion and reduced processing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional multi-step processes with intermediate under-bump metallization layers and photoresist patterning are used, then conductive structures can be formed, but manufacturing costs and lead times increase

Engineering Contradiction:
Improveconductive structure formationVSAvoidmanufacturing cost and lead time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent removes the intermediate under-bump metallization layer from the conventional process sequence, directly forming the conductive layer over the via structure. This extraction of the unnecessary intermediate layer simplifies the manufacturing process, reduces the number of processing steps, and decreases both cost and lead time while maintaining the integrity of the conductive structure formation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The via structure is pre-formed with protruding sides before the conductive layer deposition. This preliminary action creates a self-aligned template that guides the conformal deposition process, ensuring proper alignment and adhesion without requiring additional photoresist patterning steps, thereby reducing manufacturing complexity and time

Inventive Principle:
Principle #10Preliminary action

2Reliability

If conventional processes with multiple intermediate layers are used, then conductive structures can be formed, but process complexity increases

Engineering Contradiction:
Improveconductive structure formationVSAvoidprocess steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into the via structure itself: the via serves as both the conductive pathway and the self-aligned template for the conductive layer deposition. By merging these functions into a single structure, the process eliminates separate alignment and patterning steps, reducing overall process complexity while ensuring reliable conductive structure formation

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The via structure with protruding sides performs the alignment function automatically during the conformal deposition process. The geometry of the via itself provides the necessary guidance for the conductive layer formation, eliminating the need for external photoresist masks and alignment procedures, thereby simplifying the manufacturing process

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach decreases manufacturing costs and lead times by simplifying the process, promoting adhesion between conductive structures and the substrate, and enabling a higher CD/T ratio for enhanced performance.

Implementation Method 1

The use of electroless plating processes to directly form conductive layers over through vias and passivation layers

Methodology Applied
Scientific EffectElectroless plating: Electroplating

Data Source

PatentUS8847389B1Method and apparatus for a conductive bump structure
Publication Date: 2014.09.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8847389B1 patent drawing
  • US8847389B1 patent drawing
  • US8847389B1 patent drawing

AI summary

A method and apparatus for a conductive bump structure is provided. The conductive bump structure may include a conductive layer and a conductive bump formed over a through via (“TV”). The TV may be formed through a substrate and a passivation layer. The TV may have a top surface extending above a top surface of the passivation layer. The conductive layer may be formed directly over the TV using one or more electroless plating processes. The conductive layer may have sides that may taper from a top surface of the conductive layer to the top surface of the passivation layer. The conductive layer may include a plurality of layers, wherein each layer may be formed using one or more electroless plating processes. The conductive bump may be formed on the conductive layer and may be reflowed to couple the conductive bump to the conductive layer.