Electroless Plated Conductive Pillar Structure for Semiconductor Interconnects
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Solution Overview
Problem
Conventional methods for forming conductive pillars in semiconductor manufacturing are complex and costly, requiring multiple steps and intermediate layers, which increase lead time and manufacturing costs.
Innovation Solution
The use of electroless plating processes to directly form conductive pillars over interconnect pads without an intermediate under bump metallization layer or patterned photoresist, reducing the number of processing steps and materials needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form conductive pillars with intermediate under bump metallization layers and patterned photoresist, then the structural integrity and alignment precision are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the intermediate under bump metallization layer from the conventional process sequence, forming conductive pillars directly on the substrate. This extraction eliminates unnecessary process steps while maintaining alignment precision through direct electroless plating on the substrate surface, thereby reducing device complexity without sacrificing manufacturing precision
Solution Approach 2:
The substrate surface is pre-treated with a catalytic layer before electroless plating to ensure proper adhesion and uniform deposition of conductive material. This preliminary action prepares the surface in advance, eliminating the need for intermediate metallization layers while maintaining structural integrity and alignment precision
2Reliability
If multiple processing steps including intermediate layers are used, then the reliability of conductive connections is improved, but the lead time and manufacturing cost increase
Solution Approach 1:
The patent combines multiple process steps into a single integrated electroless plating operation that forms conductive pillars directly on the substrate. This merging eliminates intermediate metallization deposition and removal steps, reducing lead time while maintaining connection reliability through direct catalytic deposition that ensures strong adhesion
Solution Approach 2:
The electroless plating process is self-catalytic, where the deposited metal serves as the catalyst for further deposition. This self-service mechanism eliminates the need for external intermediate layers to facilitate deposition, reducing process time while ensuring reliable conductive connections through autonomous uniform growth
3Manufacturing precision
If conventional multi-step processes are used, then the manufacturing precision is improved, but the ease of manufacture deteriorates
Solution Approach 1:
The electroless plating process uses self-catalysis where the deposited conductive material acts as its own catalyst, enabling automatic uniform deposition without requiring complex intermediate layers or multiple processing steps. This self-service mechanism maintains pillar formation precision while dramatically simplifying the manufacturing process
Solution Approach 2:
The patent extracts and eliminates the intermediate under bump metallization layer and patterned photoresist steps from the conventional process. This extraction maintains precision through direct catalytic deposition on the substrate while significantly improving ease of manufacture by reducing the number of process steps and materials required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases manufacturing costs and lead time by simplifying the pillar formation process, allowing for more efficient integration of conductive pillars into semiconductor devices.
Implementation Method 1
forming a conductive pillar directly over the exposed portion of the interconnect pad using a catalytic an auto-catalytic chemical plating process
Data Source
AI summary
A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.