Electroless Plated Semiconductor Contact Elements
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Solution Overview
Problem
The ongoing reduction in transistor dimensions in integrated circuits leads to increased contact resistivity due to the requirement for barrier materials in tungsten-based contact technologies, which limits the operating speed of integrated circuits and results in contact failures during chemical mechanical polishing (CMP) processes.
Innovation Solution
The use of selective deposition techniques like electroless plating to form contact elements without additional barrier and seed materials, embedding the contact metal in dielectric material or using sacrificial materials to avoid mechanical stress during planarization, allowing for superior conductivity and reduced contact failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If tungsten-based contact technology with barrier materials is used, then contact elements can be formed in scaled transistor dimensions, but contact resistivity increases and operating speed decreases
Solution Approach 1:
The patent removes the barrier material layer from the contact structure, extracting the problematic intermediate layer that caused increased contact resistivity. By directly forming copper contact elements on the semiconductor surface without barrier materials, the invention achieves lower contact resistivity while maintaining compatibility with scaled transistor dimensions through precise electroless plating control
Solution Approach 2:
The invention changes the deposition method from conventional CVD tungsten to electroless plating copper, altering the material parameters and deposition mechanism. This parameter change enables direct metal-to-semiconductor contact with superior electrical properties and allows precise control of contact element dimensions through electrochemical deposition parameters
2Shape
If conventional CMP process is used for planarization, then surface flatness is achieved, but contact elements suffer from mechanical stress and contact failures occur
Solution Approach 1:
The patent replaces the mechanical CMP process with an electrochemical planarization method. By using electroless plating to form contact elements and electrochemical etching for planarization, the invention eliminates the mechanical stress and shear forces inherent in CMP that cause contact element damage, while still achieving the required surface flatness for subsequent processing
Solution Approach 2:
The invention introduces electrochemical reactions as an intermediary mechanism between material deposition and planarization. The electroless plating process and subsequent electrochemical etching use chemical mediators to achieve surface planarity without direct mechanical contact, thereby protecting the contact elements from mechanical damage while maintaining surface flatness
3Stability of the object's composition
If barrier and seed materials are added to contact structure, then adhesion and process compatibility are improved, but contact resistivity increases and conductivity decreases
Solution Approach 1:
The patent extracts and removes the barrier and seed material layers from the contact structure. By forming copper contact elements directly on the semiconductor surface through electroless plating, the invention eliminates the additional material layers that increased contact resistivity, achieving superior conductivity while maintaining adhesion through direct metal-semiconductor bonding
Solution Approach 2:
The invention achieves material homogeneity by using pure copper for contact elements without intermediate barrier or seed layers. This homogeneous copper structure extends continuously from the contact element into the conductive path, ensuring uniform electrical properties and low contact resistivity throughout the entire current path
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistivity and avoids mechanical stress during planarization, enhancing the conductivity and reliability of contact elements while preventing yield losses associated with CMP processes.
Implementation Method 1
forming a metal in a contact opening formed in a dielectric material of a contact level by performing a selective deposition process
Implementation Method 2
performing a planarization process on the basis of the laterally embedded contact element so as to provide a subsequent planar surface topography of the contact level
Data Source
AI summary
Contact elements in the contact level of a semiconductor device may be formed on the basis of a selective deposition technique, such as electroless plating, wherein an efficient planarization of the contact level is achieved without subjecting the contact elements to undue mechanical stress. In some illustrative embodiments, an overfilling of the contact openings may be reliably avoided and the planarization of the surface topography is accomplished on the basis of a non-critical polishing process. In other cases, electrochemical etch techniques are applied in combination with a conductive sacrificial current distribution layer in order to remove any excess material of the contact elements without inducing undue mechanical stress.