Electroless Plated Contact Plug Fabrication for IC Metallization
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Solution Overview
Problem
As integrated circuits become more complex, the high aspect ratio of contact openings in metallization layers becomes difficult to reliably etch and fill with conductive material, leading to manufacturing challenges and increased costs.
Innovation Solution
A self-aligned method is employed where conductive material is plated using electroless plating to reduce the aspect ratio of contact openings by 'prefilling' them, with conductive plugs formed overlying the plated material, allowing for reduced thickness and improved filling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of devices and interconnections increases to improve IC complexity, then the functionality and capability of the IC are enhanced, but the aspect ratio of contact openings increases making them difficult to etch and fill
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and depositing conductive material before the final contact opening etch. The mandrel is positioned at the bottom of the trench, and conductive material is deposited over it, creating a pre-filled structure that reduces the effective depth of the contact opening that needs to be etched and filled later, thereby reducing the aspect ratio problem
Solution Approach 2:
The contact formation process is segmented into multiple steps: forming the mandrel structure, depositing conductive material over the mandrel, etching through the ILD layer, and finally forming the contact opening. This segmentation allows each step to be optimized independently, particularly allowing the conductive material deposition to occur when the opening is more accessible
2Area of moving object
If the feature size is reduced to improve device density, then the number of devices per chip increases, but the cross sectional area of contact openings decreases more rapidly than depth, increasing aspect ratio
Solution Approach 1:
The patent applies local quality by creating a mandrel structure with specific local properties at the bottom of the trench. The mandrel provides a localized foundation that supports the conductive material and defines the contact opening geometry, allowing the contact opening to maintain adequate dimensions even as overall feature sizes are reduced for higher device density
3Ease of manufacture
If high aspect ratio contact openings are etched and filled using conventional methods, then the manufacturing process is simple, but reliability issues and increased manufacturing cost occur
Solution Approach 1:
The patent introduces a mandrel structure as an intermediary element that facilitates the contact formation process. The mandrel serves as a temporary structure that enables reliable conductive material deposition and defines the contact opening geometry, improving reliability while the additional steps are managed through systematic process integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the aspect ratio of contact openings, enhancing the reliability and cost-effectiveness of manufacturing complex integrated circuits by ensuring consistent and efficient filling of conductive material, thereby addressing the challenges of high aspect ratios.
Implementation Method 1
Conductive material is plated by electroless plating in electrical contact with the device regions and the bit lines
Data Source
AI summary
Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.