Electroless Plated Metal Pads for Wafer Bonding
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in forming metal pads suitable for bonding, where existing methods face issues with voids, steps, and waste of plating layers during electroless plating, particularly when forming thick metal pads for effective bonding between wafers.
Innovation Solution
The solution involves using electroless plating to form nonconformal metal pads on interconnect layers, eliminating the need for a catalyst layer in some cases, and incorporating barrier metal layers to reduce voids and steps, thereby optimizing the bonding process without excessive plating waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electroless plating is used to form thick metal pads for bonding, then the metal pads become suitable for bonding, but voids and steps are generated in the plating layer
Solution Approach 1:
A catalyst layer is formed in advance on the interconnect layer before electroless plating. This preliminary catalyst layer ensures uniform nucleation and growth of the metal pad during electroless plating, preventing voids and steps while enabling thick pad formation suitable for bonding.
Solution Approach 2:
A catalyst layer acts as an intermediary between the interconnect layer and the metal pad. This intermediate layer facilitates uniform deposition of the metal pad during electroless plating, eliminating defects while achieving the required thickness for effective bonding.
2Reliability
If electroless plating is used to form metal pads, then bonding is enabled, but plating layer waste occurs
Solution Approach 1:
The catalyst layer is selectively formed only in the regions where metal pads are required, rather than uniformly across the entire interconnect layer. This localized approach enables precise control of metal pad formation, reducing plating material waste while ensuring sufficient metal pad thickness for reliable bonding.
3Manufacturing precision
If a catalyst layer is used in electroless plating, then uniform metal pads are formed, but device complexity increases
Solution Approach 1:
The catalyst layer formation process is merged with the existing interconnect layer fabrication process. The catalyst layer is formed using the same patterning and deposition steps already performed for the interconnect structures, thereby adding minimal process complexity while achieving uniform metal pad formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of thick, void-reduced metal pads suited for bonding, reducing plating layer waste and improving the bonding efficiency between wafers, while avoiding the need for electric fields during plating.
Implementation Method 1
an electroless plating layer is grown on the interconnect layer
Data Source
AI summary
In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.