Electroless Plating Layer Surface Control for PCB Pattern Reliability
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Solution Overview
Problem
The miniaturization of printed wiring boards using semi-additive processes (SAP) faces challenges with pattern failure, such as short circuits and raised portions, when copper foils with smooth surfaces and small roughening particles are used for electroless plating, leading to insufficient unevenness on the electroless plating layer.
Innovation Solution
A method involving the formation of an electroless plating layer on an insulating substrate with a roughened surface, where the electroless plating layer has specific surface parameters (arithmetic mean waviness of 0.10 μm to 0.25 μm and kurtosis of 2.0 to 3.5), ensuring adequate unevenness for proper exposure and development, thereby preventing pattern failures and enhancing fine circuit formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If copper foil with smooth surface and small roughening particles is used for electroless plating, then etchability is improved, but adhesion and circuit formation reliability deteriorate
Solution Approach 1:
The invention changes the surface parameters of the electroless plating layer by controlling the arithmetic mean waviness (0.10-0.25 μm) and kurtosis (2.0-3.5) to achieve optimal balance between etchability and adhesion. This parameter optimization allows the surface to have sufficient unevenness for good adhesion while maintaining etchability for fine circuit formation.
Solution Approach 2:
The invention creates a composite surface structure on the electroless plating layer that combines controlled waviness and kurtosis characteristics. This composite surface profile provides both the adhesion benefits of unevenness and the etchability needed for fine circuits, resolving the contradiction between these two requirements.
2Strength
If copper foil with coarse roughening particles is used, then adhesion to plating circuit is improved, but etchability deteriorates
Solution Approach 1:
The invention optimizes the surface parameters by controlling arithmetic mean waviness within 0.10-0.25 μm and kurtosis within 2.0-3.5. This creates a moderate unevenness that provides sufficient adhesion strength while avoiding the excessive roughness that would hinder etching, thus resolving the contradiction between adhesion and etchability.
3Length of moving object
If electroless plating layer thickness is reduced to promote miniaturization, then circuit miniaturization is improved, but pattern failure risk increases
Solution Approach 1:
The invention changes the surface topology parameters (waviness and kurtosis) of the electroless plating layer to create an optimized surface profile. This allows thin plating layers to maintain sufficient adhesion and resist pattern failures like short circuits and raised portions, enabling circuit miniaturization without sacrificing reliability.
Solution Approach 2:
The invention performs preliminary surface profile optimization on the electroless plating layer before subsequent processing steps. By pre-establishing the optimal waviness and kurtosis values, the process prevents pattern failures during later etching and circuit formation steps, ensuring reliability even with reduced plating thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses pattern failures and improves the fine circuit forming properties by ensuring sufficient unevenness on the electroless plating layer, allowing for reduced etching and better adhesion while maintaining good etchability.
Implementation Method 1
The uneven shape of the roughening-treated surface of the roughening-treated copper foil is transferred to the laminate surface from which the roughening-treated copper foil is removed, and therefore the adhesion between the insulating layer and the plating circuit can be ensured
Implementation Method 2
Electroless copper plating 115 is applied to this roughened surface
Data Source
AI summary
There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 μm thick having a surface having an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less as measured in accordance with JIS B0601-2001 and a kurtosis Sku of 2.0 or more and 3.5 or less as measured in accordance with ISO 25178; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.