Electronic Carrier Interconnection Layout for High I/O Packaging
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Solution Overview
Problem
Quad flat non-lead packages (QFN) have limited input/output (I/O) counts, while coreless substrates or interposers with high pin counts face issues such as high costs, warpage, low yields, and long cycle times.
Innovation Solution
An electronic carrier is designed with a first interconnection structure and a second interconnection structure, where the first structure has a lower pattern density and is electrically coupled to the second structure through a non-soldering joint, allowing for heterogeneous interconnection structures to be bonded, reducing overall thickness and manufacturing costs, and enhancing heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If coreless substrates or interposers with multiple layers and high pin counts are used, then the I/O count is improved, but the cost increases, warpage issues occur, yields decrease, and cycle time increases
Solution Approach 1:
The electronic carrier is divided into a first interconnection structure with lower pattern density and a second interconnection structure with higher pattern density. This segmentation allows each structure to be optimized independently, achieving high I/O count in critical areas while maintaining manufacturing feasibility in other areas.
Solution Approach 2:
Different regions of the electronic carrier have different pattern densities tailored to local requirements. The second interconnection structure has higher pattern density where high pin counts are needed, while the first interconnection structure has lower pattern density where standard connectivity suffices, optimizing both performance and manufacturability.
2Quantity of substance
If coreless substrates or interposers with multiple layers and high pin counts are used, then the I/O count is improved, but warpage issues occur
Solution Approach 1:
The electronic carrier combines different interconnection structures with varying pattern densities and material compositions. This composite approach allows optimization of structural stability in certain regions while achieving high I/O density in others, reducing overall warpage through balanced stress distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the integration of various functions in a single electronic carrier, reduces size, increases yields, and simplifies the bonding process, while maintaining structural strength and conductivity, thus addressing the limitations of existing technologies.
Implementation Method 1
The second substrate is bonded to the first substrate through the first conductive paste
Implementation Method 2
The first interconnection structure is electrically coupled to the second interconnection structure through a first non-soldering joint between and outside of the first interconnection structure and the second interconnection structure
Implementation Method 3
The first material electrically connects the first substrate to the second substrate. The first material is cured earlier than the second material.
Data Source
AI summary
An electronic carrier and a method of manufacturing an electronic carrier are provided. The electronic carrier includes a first interconnection structure and a second interconnection structure. The first interconnection structure includes a first patterned conductive layer having a first pattern density. The second interconnection structure is laminated to the first interconnection structure and includes a second patterned conductive layer having a second pattern density higher than the first pattern density. The first interconnection structure is electrically coupled to the second interconnection structure through a first non-soldering joint between and outside of the first interconnection structure and the second interconnection structure.