Electronic Component Identification Mark for Flip-Chip Mounting Accuracy
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Solution Overview
Problem
The miniaturization of electronic component chips leads to difficulties in accurately positioning and mounting them on substrates due to the reduced dimensions between electrodes, resulting in potential misalignment and decreased joint strength, especially when using cutting line checking patterns as reference.
Innovation Solution
The implementation of a substrate with a rectangular or substantially rectangular box-shaped area featuring a plurality of electrodes and an identification mark, such as an I-shaped or L-shaped mark, which is located outside the line connecting the outer side edges of the electrodes, allows for precise placement and cutting of electronic component elements using flip-chip bonding, reducing the risk of erroneous mounting and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If electronic component chips are miniaturized to reduce size, then the electronic component becomes more compact and integration density increases, but positioning and mounting accuracy deteriorates due to reduced dimensions between electrodes
Solution Approach 1:
The patent introduces an identification mark as an intermediary reference element on the substrate. This mark serves as a mediator between the miniaturized electronic component chip and the mounting positioning system. The marking pattern provides a dedicated reference that is separate from the electrode structure, allowing the mounting apparatus to accurately locate and position the chip without being constrained by the small electrode dimensions. This intermediary reference mark enables precise positioning despite the miniaturization of the component itself.
2Ease of manufacture
If cutting line checking patterns are used for positioning, then the substrate can be cut along designated lines, but erroneous mounting occurs when electronic component chips are placed using these patterns as reference due to miniaturization
Solution Approach 1:
The patent segments the reference marking system into two distinct functional parts: (1) the cutting line checking pattern that defines where the substrate should be cut, and (2) the identification mark that provides positioning reference for mounting electronic component chips. By separating these two functions into distinct marking patterns, the patent eliminates the conflict where a single pattern had to serve both purposes. The identification mark is specifically designed for mounting positioning accuracy, while the cutting line pattern serves the cutting function, thus preventing erroneous mounting even when chips are miniaturized.
3Volume of moving object
If the dimension between electrodes is reduced for miniaturization, then component size decreases, but joint strength between bumps and electrodes deteriorates due to misalignment risk
Solution Approach 1:
The identification mark acts as an intermediary reference that enables precise alignment during the mounting process. By providing a dedicated positioning reference that is independent of the electrode dimensions, the system can accurately position the bumps relative to the electrodes even when the electrodes are very small. This intermediary reference mark ensures that the reduced electrode spacing does not lead to misalignment, thereby maintaining joint strength despite miniaturization.
Data Source
AI summary
An electronic component includes a plurality of electrodes provided in a rectangular or substantially rectangular box-shaped area on an upper surface of a substrate, an electronic component element mounted on the substrate by flip-chip bonding, and an identification mark. The identification mark is provided between a first electrode, which is arranged along one side of the rectangular or substantially rectangular box-shaped area, and a second electrode, which is adjacent to the first electrode along the one side, of the plurality of electrodes provided on the upper surface of the substrate, and is located on or outside a line connecting the outer side edges of the first and second electrodes.


