Electronic Component Sealing via Barrel Plating
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Solution Overview
Problem
Conventional methods for fabricating electronic components, particularly those using surface acoustic wave filters, face challenges in downsizing due to difficulties in dicing and sealing processes, leading to increased height and potential damage during handling, as well as positional misalignment of terminals.
Innovation Solution
A method involving the sequential cutting and separation of insulative substrates, sealing portions, and lids in a single dicing process, followed by electrolytic barrel plating to form a plated layer that covers the sealing and lid surfaces, allowing for individual component handling and reduced height, while preventing damage and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the device chip is hermetically sealed with solder on an insulative substrate, then protection from foreign matter and moisture is improved, but the component size increases and handling becomes difficult
Solution Approach 1:
The patent divides the sealing structure into multiple segments: a sealing electrode that extends from the side surface of the device chip, a sealing portion formed by soldering the sealing electrode to the insulative substrate, and a plated layer that covers the sealing portion. This segmentation allows for compact integration while maintaining hermetic sealing, thus reducing overall component size without compromising protection from foreign matter and moisture.
Solution Approach 2:
The plated layer is formed to cover the sealing portion, creating a nested structure where the plated layer envelops the sealing portion. This nesting approach allows the sealing structure to be compactly integrated within the overall component package, reducing the external dimensions while maintaining the hermetic sealing function.
2Reliability
If conventional sealing methods are used, then hermetic sealing is achieved, but the height of the component increases
Solution Approach 1:
The sealing electrode extends from the side surface of the device chip in a horizontal direction rather than vertically upward. This dimensional change allows the sealing structure to be integrated within the planar footprint of the component rather than adding to its height, achieving hermetic sealing while maintaining a low-profile configuration.
3Ease of manufacture
If conventional dicing and sealing processes are used, then sealing is achieved, but positional misalignment of terminals occurs
Solution Approach 1:
The sealing electrode is formed on the device chip before the dicing process, and the insulative substrate is prepared with corresponding electrode patterns in advance. This preliminary arrangement of sealing structures allows for precise alignment to be established before cutting, preventing positional misalignment of terminals that would otherwise occur during the dicing and sealing processes.
4Volume of moving object
If the component is downsized, then compactness is improved, but damage during handling increases
Solution Approach 1:
The patent employs a composite structure combining the device chip, sealing electrode, solder material, and plated layer. The plated layer in particular provides a robust protective coating over the sealing portion and protruding parts, enhancing mechanical strength and damage resistance. This composite construction allows the component to be downsized while maintaining sufficient durability for handling through the strengthened sealing structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the downsizing of electronic components, reduces the risk of damage during fabrication, and ensures accurate positioning of terminals, resulting in a more compact and reliable electronic component with enhanced protection against foreign matter and moisture.
Implementation Method 1
forming a plated layer covering the sealing portion by barrel plating
Data Source
AI summary
A method of fabricating an electronic component includes: mounting a device chip on an upper surface of an insulative substrate; forming a sealing portion that seals the device chip; cutting the insulative substrate and the sealing portion; and forming a plated layer covering the sealing portion by barrel plating.


