Electronic Module with Embedded Carrier and Insulation Layers

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Solution Overview

Problem

Existing electronic module technologies face challenges in forming interconnects between semiconductor chips and passive components with low parasitic inductance and improved heat dissipation, particularly in converter circuits like DC/DC, AC/DC, and AC/AC converters.

Innovation Solution

The solution involves an electronic module structure with a carrier embedded in insulation layers, where semiconductor chips with contact elements are mounted on the carrier, and thermally conductive insulation layers are used to enhance heat dissipation and reduce parasitic inductance, with a method involving multiple insulation layers and metallization for efficient interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If components are mounted as individual components on a printed circuit board, then ease of manufacture is improved, but parasitic inductance increases and heat dissipation deteriorates

Engineering Contradiction:
Improveease of manufactureVSAvoidparasitic inductance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent combines multiple components (semiconductor chips, passive components, interconnects) into a single integrated power module assembly mounted on the circuit board. This merging eliminates the need for separate component mounting and interconnect traces, thereby reducing parasitic inductance while maintaining ease of manufacture through modular assembly.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a two-dimensional layout of individual components on a circuit board to a three-dimensional integrated module structure. By stacking components and interconnects in multiple layers within a compact module, the design reduces the current path length and parasitic inductance while improving heat dissipation through vertical thermal pathways.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If components are integrated into a multi-chip module, then parasitic inductance is reduced, but heat dissipation becomes more difficult

Engineering Contradiction:
Improveparasitic inductanceVSAvoidheat dissipation
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent segments the integrated module into distinct functional layers and thermal management zones. By separating power components from control components and providing dedicated thermal pathways for each segment, the design maintains low parasitic inductance through integration while enabling effective heat dissipation through structured thermal management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces thermal interface materials and heat sink structures as intermediaries between the integrated components and the external environment. These intermediary elements facilitate heat transfer from the compact module interior to the external heat dissipation structures, resolving the heat dissipation challenge posed by integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If short interconnects are provided in the module, then parasitic inductance is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improveparasitic inductanceVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the geometric parameters of interconnects by using thick copper traces and multi-layer construction instead of thin single-layer traces. This parameter change allows for shorter interconnect paths with reduced parasitic inductance while maintaining robustness against manufacturing variations and reducing precision requirements.

Inventive Principle:
Principle #35Parameter changes

4Area of stationary object

If a compact module structure is used, then space requirements on circuit board are reduced, but electrical insulation and thermal conductivity become more difficult to maintain

Engineering Contradiction:
Improvespace requirementsVSAvoidelectrical insulation
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent uses composite material structures combining electrically insulating substrates with thermally conductive fillers and copper traces. This composite approach enables the compact module to maintain electrical insulation between different voltage domains while providing thermal pathways for heat dissipation, resolving the contradiction between compactness and functional performance.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in electronic modules with reduced parasitic inductance and improved heat dissipation, simplifying mounting and reducing space requirements on circuit boards while maintaining electrical insulation and thermal conductivity.

Implementation Method 1

thermally conductive insulation layers are used to enhance heat dissipation

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10418313B2Electronic module comprising a plurality of encapsulation layers and a method for producing it
Publication Date: 2019.09.17 INFINEON TECH AUSTRIA AG
  • US10418313B2 patent drawing
  • US10418313B2 patent drawing
  • US10418313B2 patent drawing

AI summary

An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip.