Electronic Package Layout With Auxiliary Circuit Layers for High I/O
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Solution Overview
Problem
Conventional semiconductor packages face challenges with high heat generation due to increased functional requirements, leading to higher I/O pin counts and the need for multiple circuit layers, which results in low yield and increased cost, while the use of heat sinks and heat spreaders does not adequately address these issues.
Innovation Solution
The electronic package employs a circuit structure with auxiliary circuit layers to replace some main circuit layers, reducing the number of layers needed in the package substrate, and incorporates a heat sink for efficient heat dissipation, using a core layer configuration to enhance structural strength and reduce warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of circuit layers in the package substrate is increased to meet higher I/O pin counts, then the functional requirements are satisfied, but the manufacturing yield decreases and cost increases
Solution Approach 1:
The invention divides the circuit layers into two separate parts: main circuit layers on the package substrate and auxiliary circuit layers on the circuit structure. This segmentation allows the auxiliary circuit layers to be formed on a separate substrate and then bonded to the package substrate, enabling high I/O pin counts without increasing the layer count on the package substrate itself, thereby maintaining manufacturing yield.
Solution Approach 2:
The invention transitions from a single-substrate multi-layer approach to a multi-substrate stacked approach. By adding the auxiliary circuit layers on a separate circuit structure and bonding it to the package substrate, the solution moves from increasing layers in one dimension to adding functional capacity in another dimension (separate substrate stacking), thus achieving high I/O pin counts without compromising yield.
2Adaptability or versatility
If more circuit layers are added to the package substrate to increase I/O pin count, then functional requirements are met, but the overall cost increases
Solution Approach 1:
By segmenting the circuit layers into main and auxiliary parts on separate substrates, the invention enables independent optimization of each substrate's manufacturing process. This allows the package substrate to maintain a cost-effective layer count while the auxiliary circuit structure provides the additional I/O capacity, reducing overall manufacturing cost compared to creating a single high-layer-count substrate.
Solution Approach 2:
The invention merges two separately manufactured substrates (package substrate with main circuit layers and circuit structure with auxiliary circuit layers) into a single integrated package module. This merging allows each substrate to be manufactured independently at optimal costs and then combined through bonding, achieving high I/O pin counts at lower overall cost than manufacturing a single multi-layer substrate.
3Adaptability or versatility
If the package substrate has multiple circuit layers, then high I/O pin counts are achieved, but the structural strength decreases and warpage increases
Solution Approach 1:
By segmenting the circuit layers onto separate substrates, the invention maintains thin, structurally strong individual substrates rather than creating a thick, multi-layer substrate prone to warpage. The bond between substrates provides structural reinforcement, and each substrate can be optimized for strength while collectively providing high I/O pin capacity.
Solution Approach 2:
The invention resolves the structural weakness issue by moving from increasing layers in the vertical dimension (which causes warpage) to adding functional capacity through horizontal stacking of separate substrates. This dimensional transition allows each substrate to remain thin and strong while the assembly provides the required I/O pin count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves yield and reduces overall cost by minimizing the number of package substrate layers, allows for thinner and smaller designs, and maintains structural integrity, while maintaining high I/O pin counts and heat dissipation capabilities.
Implementation Method 1
heat generated by the semiconductor chip is conducted to the top plate 130 of the heat sink 13 via the non-active surface 11b and the heat-dissipating paste 12
Implementation Method 2
The heat sink is usually bonded to the back of the chip by a heat-dissipating paste such that heat generated by the semiconductor chip can be dissipated by the heat-dissipating paste and the heat sink
Data Source
AI summary
Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.