Electronic Package Auxiliary Circuit Layers for Higher I/O Yield

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Solution Overview

Problem

The increasing demand for higher density electronic components and functional requirements in semiconductor chips leads to a substantial increase in the number of circuit layers in semiconductor packages, resulting in low yield and high costs due to the complexity of manufacturing multiple-layer substrates.

Innovation Solution

The electronic package design incorporates a circuit structure with auxiliary circuit layers that replace some of the main circuit layers, reducing the number of main circuit layers needed and improving yield and cost-effectiveness, while maintaining structural strength and heat dissipation capabilities through a heat sink configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of main circuit layers is increased to meet functional requirements, then the I/O pin capacity and circuit complexity are improved, but the manufacturing yield decreases and cost increases

Engineering Contradiction:
ImproveI/O pin capacityVSAvoidmanufacturing yield
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides the circuit layers into two separate segments: main circuit layers on the package substrate and auxiliary circuit layers on the circuit structure. This segmentation allows the auxiliary circuit layers to handle additional I/O requirements without increasing the complexity of the main circuit layers, thereby maintaining manufacturing yield while improving I/O capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extends the circuit structure vertically beyond the package substrate, creating an additional dimensional space for auxiliary circuit layers. This allows circuit functionality to be expanded in the vertical dimension rather than increasing horizontal layer complexity on the substrate, thus improving adaptability without compromising manufacturing reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the number of main circuit layers is increased to accommodate more functions, then the functional requirements are met, but the manufacturing cost increases due to low yield

Engineering Contradiction:
Improvefunctional requirementsVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

By segmenting circuit functions between main and auxiliary layers, the patent reduces the complexity of the main circuit layers that require precise substrate manufacturing. This segmentation lowers manufacturing difficulty and cost while still meeting comprehensive functional requirements through the combined circuit structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit structure acts as an intermediary between the package substrate and the electronic component, providing auxiliary circuit layers that extend functionality without requiring the substrate itself to be more complex. This intermediary approach meets functional requirements while keeping substrate manufacturing simple and cost-effective.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If more main circuit layers are used to increase I/O capacity, then the circuit functionality is improved, but the package thickness and complexity increase

Engineering Contradiction:
ImproveI/O capacityVSAvoidpackage structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the circuit architecture into a standardized package substrate with main layers and a separate circuit structure with auxiliary layers. This segmentation organizes the complexity into manageable modules, improving I/O capacity while controlling overall package complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes the vertical dimension by extending the circuit structure beyond the substrate boundaries. This allows additional circuit layers to be added in the vertical direction rather than increasing horizontal substrate layer count, thereby improving I/O capacity while maintaining a compact and organized package structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the number of layers in the package substrate, improving yield and reducing overall costs, while maintaining the required functional specifications and structural integrity, and allows for a thinner and more compact package design.

Implementation Method 1

heat generated by the semiconductor chip is conducted to the top plate 130 of the heat sink 13 via the non-active surface 11b and the heat-dissipating paste 12 to dissipate heat to the outside of the semiconductor package 1

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS12051641B2Electronic package and manufacturing method thereof
Publication Date: 2024.07.30 SILICONWARE PRECISION IND CO LTD
  • US12051641B2 patent drawing
  • US12051641B2 patent drawing
  • US12051641B2 patent drawing

AI summary

Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.