Electronic Package Dielectric Layout for Bridge Alignment and Low Stress

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Solution Overview

Problem

Conventional electronic packaging methods using molding compounds to cover bridge elements and chips result in alignment shifts and stress due to thermal expansion coefficient differences, leading to reliability issues and suboptimal signal transmission.

Innovation Solution

A manufacturing method employing a silicate composite material or materials suitable for chemical-mechanical polishing for the base and intermediate dielectric layers, along with direct copper bonding of bridge elements to chips, to reduce interface stress and enhance signal transmission efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If molding compound is used to cover bridge element and chips, then protection is provided, but alignment shift occurs and stress accumulates due to thermal expansion coefficient difference

Engineering Contradiction:

Improveprotection of chips and bridge elementVSAvoidalignment of chips

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the material parameter of the dielectric layer from conventional molding compound to a material with thermal expansion coefficient matching the chip material. This parameter change eliminates the thermal expansion mismatch, preventing both alignment shifts during curing and stress accumulation during thermal cycles, while still providing the required protection function.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If molding compound is used to cover bridge element and chips, then protection is provided, but stress accumulates on contact surface due to thermal expansion coefficient difference

Engineering Contradiction:

Improveprotection of chips and bridge elementVSAvoidstress on contact surface

Core Design Contradiction:

ReliabilityVSStress or pressure

Solution Approach 1:

The patent changes the material parameter of the dielectric layer from conventional molding compound to a material with thermal expansion coefficient matching the chip material. This parameter change eliminates the thermal expansion mismatch, preventing stress accumulation on the contact surface between chips and the dielectric layer during thermal curing and operational cycles.

Inventive Principle:

Principle #35Parameter changes

3Speed

If bridge element overlaps with adjacent chips, then signal transmission path is shortened, but alignment precision is required

Engineering Contradiction:

Improvesignal transmission speedVSAvoidalignment of bridge element with chips

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent changes the material parameter of the dielectric layer to match the thermal expansion coefficient of the chips. This eliminates stress and alignment shifts during thermal curing, thereby maintaining the precise alignment between the bridge element and chips. The short signal transmission path achieved through overlapping is thus preserved without suffering from misalignment issues.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes chip warpage, improves signal transmission performance, and increases power efficiency by reducing circuit power consumption and enhancing bridging density, resulting in a high-reliability electronic package suitable for high-performance computing applications.

Implementation Method 1

A material of the base dielectric layer includes a silicate composite material or a material suitable for chemical-mechanical polishing... The material of the base dielectric layer and the material of the intermediate dielectric layer can reduce the interface stress between the material and each chip

Methodology Applied

Scientific EffectThermal expansion coefficient matching: Thermal Expansion

Implementation Method 2

An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed... The intermediate dielectric layer is disposed on the chips and the base dielectric layer and surrounds the at least one bridge element

Methodology Applied

Scientific EffectMechanical support and stress distribution:

Implementation Method 3

Multiple bridging pads of the bridge element are respectively bonded to multiple first chip pads of the active surfaces of the adjacent chips... the direct copper bond of the bridge element to the chips also helps to drastically improve transmission performance

Methodology Applied

Scientific EffectDirect copper bonding: Welding

Data Source

PatentUS20240421124A1Manufacturing method of electronic package and electronic package

Publication Date: 2024.12.19 VIA TECH INC

AI summary

A manufacturing method of an electronic package includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each chip is fixed to a back surface temporary carrier via a back surface temporary bonding layer. A base dielectric layer surrounds each chip and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material. At least one bridge element is installed on the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. Multiple intermediate conductive vias and a redistribution structure are respectively formed on the chips and the intermediate dielectric layer. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed. An electronic package produced by the manufacturing method is also provided.