Electronic Package Layout Using Conductive Pillars to Cut TSV Count

The patent divides the through silicon interposer into multiple smaller interposer boards. Each smaller interposer board has fewer through-silicon vias, reducing the fabrication complexity and increasing yield. The smaller interposer boards are then arranged and bonded to the package substrate in a matrix pattern to achieve the required total bonding area. This segmentation approach allows the system to scale up the bonding area without proportionally increasing the complexity of fabricating each individual interposer.

By dividing the large interposer into multiple smaller interposer boards, the thermal mass and thermal stress concentration are reduced. Each smaller interposer experiences more uniform thermal expansion, and the gaps between them allow for stress relief. This segmentation prevents the warpage issues that occur in large monolithic interposers with mismatched CTE between the interposer, encapsulant, and package substrate.

The fabrication of multiple smaller interposer boards with fewer through-silicon vias can be performed in parallel rather than sequentially drilling and filling a large number of vias in one large interposer. This segmentation enables concurrent processing, reducing the overall fabrication time. Additionally, the smaller interposers can be fabricated using standard processes without requiring excessive aspect ratio control that would slow down production.

Dividing the interposer into multiple smaller boards reduces the total number of through-silicon vias that need to be fabricated, as each smaller interposer has fewer vias. This reduces material consumption (silicon, copper, dielectric materials) and processing costs. The smaller interposers can also be fabricated using more cost-effective processes without the need for precise aspect ratio control required in large interposers with deep vias.