Electronic Package Structure Using Conductive Pillars to Cut TSV Load
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Solution Overview
Problem
The increasing complexity of electronic products requires larger bonding areas and more through-silicon vias, leading to fabrication challenges, thermal stress issues, and reduced reliability due to mismatched thermal expansion coefficients, resulting in warpage, poor bonding, and increased costs.
Innovation Solution
The introduction of an encapsulating layer with conductive pillars and a smaller interposer board with through-silicon vias, where the conductive pillars act as an electric transmission path for power or ground functions, reducing the number of through-silicon vias and using an encapsulating layer with matched thermal expansion coefficients to alleviate thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the bonding area and number of through-silicon vias are increased to meet complex electronic product requirements, then the electrical connectivity and functionality are improved, but the fabrication time and cost increase, and the yield decreases
Solution Approach 1:
The patent divides the through-silicon via structure into two types: conventional TSVs for signal transmission and new micro-vias for power/ground transmission. This segmentation allows different fabrication processes for different via types, reducing overall fabrication complexity and improving yield while maintaining electrical connectivity.
Solution Approach 2:
The patent applies different via structures and fabrication methods to different functional areas: signal areas use conventional TSVs with specific aspect ratios, while power/ground areas use micro-vias with different characteristics. This local differentiation optimizes each area for its specific function while reducing overall fabrication difficulty.
2Adaptability or versatility
If the bonding area and number of through-silicon vias are increased, then the electrical connectivity is improved, but the fabrication cost increases
Solution Approach 1:
The patent segments the via fabrication into two distinct processes: conventional TSV fabrication for signals and simpler micro-via fabrication for power/ground. This reduces the need for expensive, complex fabrication steps across the entire interposer, lowering overall manufacturing cost while maintaining connectivity.
Solution Approach 2:
The patent uses a cost-effective approach by employing simpler micro-via structures for power/ground transmission instead of expensive conventional TSVs. These micro-vias are optimized for their specific function and can be fabricated more economically, reducing overall manufacturing cost.
3Adaptability or versatility
If the volume of the through silicon interposer is increased to provide larger bonding area, then the electrical connectivity is improved, but the thermal stress distribution becomes uneven due to CTE mismatch, resulting in warpage and reliability issues
Solution Approach 1:
The patent segments the interposer into regions with different via types: conventional TSVs in signal areas and micro-vias in power/ground areas. This segmentation allows optimized thermal management for each region, improving overall thermal stress distribution uniformity while maintaining large bonding area.
Solution Approach 2:
The patent changes the via structure parameters (size, depth, material composition) based on functional requirements. Micro-vias have different aspect ratios and materials compared to conventional TSVs, allowing optimization of thermal conductivity and CTE matching in different regions to reduce warpage.
Data Source
AI summary
An electronic package is provided. The electronic package includes an encapsulating layer encapsulating a plurality of conductive pillars and an interposer board that has through-silicon vias. An electronic component is disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias. The conductive pillars act as an electric transmission path of a portion of electric functions of the electronic component. Therefore, the number of the through-silicon vias is reduced, and the fabrication time and chemical agent cost are reduced. Also, the through silicon interposer of a large area can be replaced by a smaller one, and the yield is increased. Further, a method of fabricating an electronic package is provided.