Dual-Sided Electronic Package Structure for Fine-Pitch Isolation

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Solution Overview

Problem

Existing semiconductor packages with wafer-level packaging techniques have limited functionality and performance due to semiconductor elements being disposed on only one side of the circuit structure, restricting the integration of additional components and enhancing performance.

Innovation Solution

A method involving a carrying board with an insulation layer, conductive pillars, and encapsulation layers to embed and connect multiple electronic components on both sides of the circuit structure, allowing for enhanced functionality and performance by exposing end surfaces of conductive pillars for external contacts and precise pitch control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If semiconductor elements are disposed on only one side of the circuit structure using WLP technique, then the manufacturing process is simplified, but the functionality and performance of the electronic package are limited

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidfunctionality and performance
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent transitions from a single-sided component arrangement to a dual-sided arrangement by utilizing the vertical dimension. Electronic components are disposed on both the first surface (via conductive pillars) and second surface (via conductive bumps) of the circuit structure, effectively using three-dimensional space to increase functionality without complicating the fundamental manufacturing process

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple electronic components are integrated on both sides of the circuit structure, then functionality and performance are enhanced, but the risk of conductive element bridging increases

Engineering Contradiction:
Improvefunctionality and performanceVSAvoidconductive element bridging risk
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies different local quality characteristics to different regions of the circuit structure. The first surface uses conductive pillars with specific electrical properties, while the second surface uses conductive bumps with different properties. This localized differentiation allows multiple components to be integrated on both sides while maintaining electrical isolation and preventing bridging between different conductive elements

Inventive Principle:
Principle #3Local quality

3Productivity

If fine-pitch applications are implemented with multiple conductive elements, then device density is increased, but the difficulty of preventing conductive element bridging increases

Engineering Contradiction:
Improvedevice densityVSAvoidconductive element bridging prevention
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements local quality by assigning different conductive structures to different pitch requirements. Conductive pillars are used where precise alignment and electrical connection are critical, while conductive bumps are used where mechanical compliance and solderability are more important. This local differentiation enables fine-pitch applications to achieve high device density without increasing the complexity of bridging prevention

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The circuit structure itself acts as an intermediary between the conductive pillars and conductive bumps. By routing connections through the circuit structure's conductive layers and vias, the patent provides controlled pathways that prevent direct bridging between conductive elements on opposite surfaces, enabling fine-pitch configurations with maintained reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12176327B2Method for fabricating electronic package
Publication Date: 2024.12.24 SILICONWARE PRECISION IND CO LTD
  • US12176327B2 patent drawing
  • US12176327B2 patent drawing
  • US12176327B2 patent drawing

AI summary

An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.