Electronic Package Interlayer for Thermal Stress Delamination

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Solution Overview

Problem

Conventional electronic device packages suffer from delamination due to thermal stress caused by mismatched material characteristics between molding compounds and metals during thermal cycles, which deteriorates their reliability.

Innovation Solution

Incorporating a buffer layer with a lower elastic modulus than both the redistribution layer and the encapsulation layer, strategically positioned between them to alleviate stress and reduce thermal expansion differences, thereby mitigating delamination risks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If different materials (molding compound and metal) are used in the electronic device package, then the functional requirements are met, but thermal stress occurs during thermal cycles causing delamination

Engineering Contradiction:
Improvematerial compatibilityVSAvoiddelamination resistance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

An interlayer is introduced between the molding compound layer and the metal patterned layer to serve as a stress buffer. This intermediary layer has an elastic modulus lower than both adjacent layers, allowing it to absorb thermal stress and prevent direct stress transmission that would cause delamination at the interface between dissimilar materials.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The elastic modulus parameter of the interlayer is specifically selected to be lower than both the molding compound layer and the metal patterned layer. This parameter optimization creates a gradient structure that gradually transitions between materials of vastly different stiffness, reducing thermal stress concentration and preventing delamination during thermal cycling.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a buffer layer with lower elastic modulus is inserted between the RDL and encapsulation layer, then stress is alleviated and delamination is reduced, but the device complexity increases

Engineering Contradiction:
Improvedelamination resistanceVSAvoidlayer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The package structure is segmented into distinct functional layers with the interlayer positioned specifically between the metal RDL and the molding compound encapsulation layer. This segmentation allows each layer to be optimized for its specific function while managing the interface stresses between dissimilar materials.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The buffer layer effectively reduces delamination risk, enabling the electronic device package to withstand over 2000 thermal cycle tests without failure, enhancing the package's reliability and longevity.

Implementation Method 1

The interlayer is shaped and sized to reduce a difference between a first thermal expansion of the patterned conductive layer and a second thermal expansion of the encapsulation under a change of temperature

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

An elastic modulus of the interlayer is less than an elastic modulus of the RDL and an elastic modulus of the encapsulation layer

Methodology Applied
Scientific EffectElasticity: Elasticity

Data Source

PatentUS12027469B2Electronic device package and method of manufacturing the same
Publication Date: 2024.07.02 ADVANCED SEMICON ENG INC
  • US12027469B2 patent drawing
  • US12027469B2 patent drawing
  • US12027469B2 patent drawing

AI summary

An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.