Double-Sided Electronic Package With Miniaturized Support Structures
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Solution Overview
Problem
Conventional semiconductor packages are limited by the height of conductive pillars, restricting the arrangement of electronic elements of different specifications and increasing layout areas, making it difficult to integrate multiple functional elements within a single package structure.
Innovation Solution
A double-sided packaging design with a carrier structure having a routing layer and support structures, allowing for a layout width less than the carrier structure, enabling an accommodating space for additional elements, and utilizing a cladding layer for encapsulation and miniaturized support structures to increase packaging density and structural strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the height of conductive pillars is increased to accommodate semiconductor chips with higher height, then the accommodating capability for different specifications is improved, but the layout area of conductive pillars increases, making it difficult to add other electronic elements
Solution Approach 1:
The patent transitions from a single-sided packaging structure to a double-sided packaging structure, utilizing the third dimension (vertical stacking) to accommodate electronic elements. The circuit structure is stacked on the carrier structure via support structures, allowing electronic elements to be arranged on both the first and second sides of the carrier structure, thereby increasing packaging density without expanding the layout area of individual support structures.
Solution Approach 2:
The patent divides the packaging structure into multiple independent layers: carrier structure, support structures, circuit structure, and cladding layer. This segmentation allows each component to be optimized independently - the support structures can be miniaturized while the overall packaging capacity is increased through vertical stacking of multiple layers.
2Strength
If the width of conductive pillars is increased to support higher height chips, then the structural strength is improved, but the layout areas increase, reducing the space for other electronic elements
Solution Approach 1:
The support structures are formed using composite materials including copper core balls with solder material coatings. This composite structure provides high structural strength with minimal dimensions, as the copper core offers excellent mechanical strength while the solder coating provides bonding capability, allowing miniaturized support structures to achieve both strength and functionality.
Solution Approach 2:
The patent changes the material parameters of support structures by using copper core balls with controlled sizes (0.1mm to 0.5mm diameter). By optimizing the size and material composition parameters, the support structures achieve sufficient structural strength while maintaining minimal layout area, enabling high-density packaging.
3Device complexity
If conventional single-sided packaging is used, then the structure is simple, but the packaging density is limited and multiple functional elements cannot be integrated
Solution Approach 1:
The patent implements double-sided packaging by stacking the circuit structure on the carrier structure via support structures, utilizing vertical space to arrange electronic elements on both sides. This three-dimensional arrangement significantly increases packaging density while maintaining relatively simple structural complexity, as each layer can be processed independently.
Solution Approach 2:
The patent employs a nested structure where the circuit structure is stacked on the carrier structure, and the cladding layer encapsulates both structures. This nesting approach allows multiple functional elements to be integrated within a compact volume, achieving high packaging density without proportionally increasing structural complexity.
Data Source
AI summary
An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.


