Electronic Package Routing Structure for Fine-Pitch I/O
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Solution Overview
Problem
Conventional semiconductor packages face increased manufacturing difficulty and cost due to finer pitch requirements for conductive bumps, leading to reduced yield as the number of integrated semiconductor chips increases, necessitating more routing layers and finer line specifications.
Innovation Solution
A semiconductor package design featuring a coreless routing structure with a circuit member having a greater vertical projected area than the carrier structure, allowing for reduced layer count and enhanced structural strength through a cladding layer, and a routing design that replaces a portion of the carrier structure's circuit layers, facilitating electrical connections between electronic elements via the circuit member.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of integrated semiconductor chips is increased to achieve higher computing power and I/O expansion, then the functional capability is improved, but the pitch between conductive bumps decreases requiring finer line specifications and more routing layers which increases manufacturing difficulty and cost
Solution Approach 1:
The patent divides the routing function into two parts: the carrier structure provides basic routing layers, while the circuit member provides additional routing layers. This segmentation allows each component to have optimized routing without requiring the entire package to use fine-pitch routing specifications, thereby reducing manufacturing complexity while maintaining high functional capability
Solution Approach 2:
The patent introduces a third dimension by stacking the circuit member on top of the carrier structure. This vertical arrangement allows routing signals to travel through multiple layers in the Z-direction, reducing the need for lateral routing on single layers and enabling higher I/O density without proportionally increasing manufacturing difficulty
2Reliability
If more routing layers are added to the carrier structure to accommodate increased I/O requirements, then the electrical connectivity is improved, but the manufacturing cost and difficulty increase significantly
Solution Approach 1:
The patent merges the routing functions of both the carrier structure and circuit member into a unified electrical connection system. The circuit layers in the carrier structure and the circuit layers in the circuit member work together to provide complete routing paths, distributing the routing burden across both components rather than requiring all routing layers to be in one expensive fine-pitch structure
Solution Approach 2:
The patent applies different routing densities to different regions: the carrier structure uses coarser pitch routing for less demanding connections, while the circuit member uses finer pitch routing only where high-density I/O is required. This local optimization reduces overall manufacturing cost while maintaining necessary electrical connectivity
3Productivity
If the circuit member has the same or larger vertical projected area than the carrier structure, then the routing capacity is maximized, but the structural strength decreases and warpage issues occur
Solution Approach 1:
The patent concentrates the high-density routing capacity in the circuit member which has smaller projected area, while the carrier structure maintains larger area for structural support. This local concentration of routing function allows the majority of the package structure to be optimized for strength and warpage resistance
4Quantity of substance
If finer pitch specifications are used for the fan-out redistribution layer circuit structure to accommodate more conductive bumps, then the I/O density is improved, but the manufacturing precision requirements increase leading to reduced yield
Solution Approach 1:
The patent segments the I/O density requirement between the carrier structure and circuit member. The carrier structure handles routing with coarser pitch specifications that are easier to manufacture with high yield, while the circuit member provides the additional routing layers needed for high I/O density. This segmentation allows achieving high I/O density without requiring the entire structure to use difficult-to-manufacture fine-pitch specifications
Data Source
AI summary
A method of manufacturing an electronic package is provided and includes disposing a circuit member and a plurality of electronic elements on opposite sides of a carrier structure having circuit layers respectively, so that any two of the plurality of electronic elements can be electrically connected to each other via the circuit layers and the circuit member, where a vertical projected area of the carrier structure is larger than a vertical projected area of the circuit member, such that the circuit member is free from being protruded from side surfaces of the carrier structure. Therefore, the circuit member replaces a part of circuit layers of the carrier structure to reduce the difficulty of fabricating the circuit layers in the carrier structure.