Electronic Package Stacking for Compact Short-Path Interconnects
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Solution Overview
Problem
Conventional electronic packages face challenges in achieving miniaturization and low power consumption while maintaining high electrical performance due to limited space for auxiliary functional components, leading to increased manufacturing costs and inefficient signal transmission.
Innovation Solution
The electronic package incorporates an encapsulation layer with conductive pillars and an embedded electronic structure that allows for close-range connection with auxiliary components, eliminating the need for redesigning the package and expanding component sizes, and features a manufacturing method that forms conductive and insulating layers to facilitate efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If auxiliary functional components are directly provided on the circuit board, then the transmission distance is long resulting in degraded electrical functions and increased power consumption, but the volume of the end product cannot fulfill the requirements of light, thin and compact products
Solution Approach 1:
The patent transitions from planar arrangement on the circuit board to three-dimensional stacking architecture. The auxiliary functional component is integrated into a separate package structure that stacks vertically with the processor chip, utilizing the Z-axis dimension. This dimensional change enables both shortened transmission paths (improving power consumption) and compact form factor (reducing volume), as the components occupy vertical space rather than expanding the circuit board area.
Solution Approach 2:
The patent implements nesting by integrating the auxiliary functional component within the package structure that encapsulates the processor chip. The package substrate, encapsulant, and auxiliary component are nested together in a hierarchical arrangement where the auxiliary component resides within the same package envelope as the processor, achieving space efficiency while maintaining short electrical connections.
2Use of energy by moving object
If auxiliary functional component is integrated to the lower side of the package substrate, then the transmission distance is shortened reducing power consumption, but there is not enough room for more auxiliary functional components
Solution Approach 1:
The patent resolves the space limitation by utilizing the vertical dimension through multi-layer stacking. Instead of being constrained to the two-dimensional lower side of the package substrate, the system stacks additional functional layers vertically. The encapsulant and auxiliary functional components are arranged in multiple vertical levels, enabling integration of multiple components without increasing the footprint area, thus maintaining short transmission paths while increasing component capacity.
Solution Approach 2:
The patent segments the package structure into multiple functional layers stacked vertically. Each layer can contain different functional components (processor chip, auxiliary functional components, passive components), allowing independent optimization and integration of multiple functions. This segmentation enables the system to accommodate multiple auxiliary functional components by distributing them across different vertical layers rather than crowding them on a single plane.
3Reliability
If semiconductor chips are disposed on the package substrate, then the electrical connection is achieved, but the surface area and volume of the circuit board increases
Solution Approach 1:
The patent employs three-dimensional stacking architecture where semiconductor chips and auxiliary components are arranged vertically rather than spread out on the circuit board surface. The package substrate with stacked components is mounted on the circuit board, utilizing the vertical dimension to achieve all electrical connections within a compact footprint. This eliminates the need for large surface area while maintaining reliable electrical connectivity through vertical interconnects.
Solution Approach 2:
The patent nests multiple semiconductor chips and auxiliary functional components within a compact package structure that is then mounted on the circuit board. The package substrate encapsulates and organizes multiple components in a nested arrangement, concentrating all necessary electrical connections within a small volume. This nesting approach achieves full electrical functionality while minimizing the surface area occupied on the circuit board.
Data Source
AI summary
An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.