Electronic Package Pre-Cutting to Reduce Fan-Out Warpage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional fan-out packaging processes face warpage issues due to thermal expansion coefficient inconsistencies and stress unevenness, leading to fabrication challenges and yield problems.

Innovation Solution

A method involving pre-cutting processes on cutting paths where maximum stress occurs, removing routing and encapsulating layers to reduce warpage, using laser cutting or etching, and bonding a second carrier structure to a routing structure after removing the first carrier.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional fan-out packaging process is performed on monolithic wafer structure, then multi-chip/high number of circuit layers/large fan-out size/high heat dissipation requirements are met, but warpage problems occur due to thermal expansion coefficient inconsistency and stress unevenness

Engineering Contradiction:
Improvemulti-chip/high number of circuit layers/large fan-out size/high heat dissipation design capabilityVSAvoidwafer flatness
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent divides the monolithic wafer structure into multiple independent packaging units by introducing cutting paths. Each packaging unit can be processed and handled separately, reducing the overall size and stress accumulation. The segmentation allows the wafer to be divided into manageable sections that can be loaded into fabrication machines without excessive warpage, while still maintaining the multi-chip and high circuit layer capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary cutting operations to create cutting paths between packaging units before final singulation. This preliminary action reduces stress accumulation and prevents warpage from becoming excessive during subsequent processing steps. By pre-establishing separation paths, the wafer structure maintains better flatness during fabrication while enabling the complex multi-chip architectures.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If complete singulation is performed early to separate packaging structures, then individual package processing is enabled, but yield is reduced due to warpage occurring in subsequent processes

Engineering Contradiction:
Improveindividual package processing capabilityVSAvoidfabrication yield
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent performs preliminary cutting to create separation paths while keeping packaging units connected through the carrier structure. This allows individual package processing to begin earlier in the fabrication sequence while maintaining structural support that prevents warpage. The preliminary cuts enable easier handling and processing of individual units without the risk of excessive warpage that would occur if complete singulation were performed too early.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent retains the carrier structure and performs intermediate cutting operations that provide mechanical support and cushioning during subsequent fabrication steps. This beforehand cushioning prevents warpage from developing to critical levels that would cause yield loss, while still enabling individual package processing operations to be performed on separated units.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Manufacturing precision

If cutting paths are introduced between packaging structures, then warpage is reduced by removing stress concentration areas, but additional process steps are required

Engineering Contradiction:
Improvewafer flatnessVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces cutting paths that segment the monolithic wafer into discrete packaging units. This segmentation reduces stress concentration and prevents warpage by creating natural stress relief zones. The cutting paths are strategically positioned between packaging structures, allowing the wafer to maintain flatness during fabrication while requiring only standard cutting operations that can be integrated into existing fabrication processes.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces warpage phenomena and avoids yield issues in subsequent processes without requiring new materials or equipment, maintaining existing processes and machinery.

Implementation Method 1

the pre-cutting process removes the routing structure and the encapsulating layer on at least one cutting path by laser cutting

Methodology Applied
Scientific EffectLaser cutting: Laser Ablation

Implementation Method 2

bonding a second carrier structure onto the routing structure

Methodology Applied
Scientific EffectBonding: Welding

Data Source

PatentUS20250266393A1Method for fabricating electronic package
Publication Date: 2025.08.21 SILICONWARE PRECISION IND CO LTD
  • US20250266393A1 patent drawing
  • US20250266393A1 patent drawing
  • US20250266393A1 patent drawing

AI summary

A method for fabricating an electronic package is provided, which mainly provides a first carrier structure on which a plurality of packaging structures are disposed and a cutting path is provided between each of the packaging structures, wherein each of the packaging structures has a circuit structure disposed on the first carrier structure, an electronic component disposed on the circuit structure, an encapsulating layer disposed the circuit structure and encapsulating the electronic component, and a routing structure disposed on the encapsulating layer; a pre-cutting process is performed to remove the routing structure and encapsulating layer above the cutting path to reduce warpage phenomenon, thereby avoiding yield problems in the subsequent process; and a second carrier structure is bonded onto the routing structure and the first carrier structure is removed.