Electronic Package Structure for CTE-Induced Warpage Suppression
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Solution Overview
Problem
Conventional semiconductor packages face issues with warpage due to mismatched coefficients of thermal expansion (CTE) between encapsulants and semiconductor chips, leading to cracks and low product yield during packaging processes like reflow or testing.
Innovation Solution
The introduction of a dummy die and a bonding layer configuration, where the dummy die is spaced apart from the electronic element and bonded with a thicker second bonding layer, helps to disperse stress and reduce the volume ratio of the encapsulation layer, preventing warpage and improving coating conditions for the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the encapsulant is used as a panel with wafer form to cover multiple semiconductor chips, then the packaging can achieve high-density integration and increased I/O, but the encapsulant is likely to warp due to CTE mismatch between the encapsulant and semiconductor chips during temperature cycling or stress changes
Solution Approach 1:
A carrier is introduced as an intermediary substrate to support the encapsulant panel during the packaging process. The carrier provides mechanical stability and prevents warpage by serving as a rigid backing that counteracts the CTE mismatch stresses between the encapsulant and semiconductor chips during temperature cycling and reflow processes.
Solution Approach 2:
The carrier is positioned beforehand to support the encapsulant panel before warpage can occur. This preventive measure cushions the encapsulant against thermal and mechanical stresses during subsequent processing steps such as reflow soldering and temperature cycling, preventing cracks and maintaining package integrity.
2Reliability
If the encapsulant is subjected to reflow oven process or dropping test, then the semiconductor package can achieve proper solder joint formation and reliability testing, but cracks occur between the semiconductor chips and encapsulant due to warpage
Solution Approach 1:
The carrier acts as a mediator that protects the chip-encapsulant interface during reliability testing. By providing continuous support to the encapsulant panel, the carrier prevents the formation of gaps and stress concentrations that would otherwise lead to cracking at the chip-encapsulant bonds during dropping tests and thermal cycling.
Solution Approach 2:
The carrier provides beforehand cushioning to the encapsulant panel, preventing cracks from forming at the chip-encapsulant interfaces before reliability testing begins. This protective support ensures that the solder joints and chip bonds remain intact during subsequent reflow and dropping tests, achieving both solder joint reliability and maintaining bond strength.
3Stability of the object's composition
If a dummy die is added to the package structure to suppress warpage, then the encapsulant warpage is reduced, but the device complexity increases
Solution Approach 1:
Instead of adding a dummy die, the carrier serves as an intermediary that achieves warpage suppression without increasing package structure complexity. The carrier is removed after the encapsulant is released from the semiconductor chips, so it does not become part of the final package structure, thus maintaining simplicity while achieving the desired flatness.
Solution Approach 2:
The carrier is a temporary, disposable component used only during the packaging process. It performs the critical function of preventing warpage during manufacturing but is discarded afterward, avoiding the need for permanent additions like dummy dies that would increase device complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses warpage, enhances product reliability by exposing a surface with better roughness for subsequent processes, and reduces the volume of the encapsulation layer, thereby improving anti-warping performance and yield.
Implementation Method 1
a first bonding layer embedded in the encapsulation layer and bonded on the inactive surface, wherein an outer surface of the first bonding layer is flush with the second surface of the encapsulation layer
Implementation Method 2
the encapsulant 15 is likely to be warped due to the mismatch of the coefficient of thermal expansion (CTE) between the encapsulant 15 and the semiconductor chips 11
Data Source
AI summary
An electronic package includes a first electronic element and a dummy die embedded in an encapsulation layer, where the dummy die is used to prevent a warpage caused by the mismatch of coefficient of thermal expansion (CTE) between the encapsulation layer and the first electronic element in the manufacturing process of large full-panel.