Electrooptic Device Gate Electrode Overlap Layout Reduces Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electrooptic devices, the increase in transistor size and parasitic capacitance due to pitch reduction leads to higher push down voltage and power consumption, causing heat generation issues.
Innovation Solution
The electrooptic device design includes a scan line and data lines with a specific layout where the gate electrode of one transistor overlaps a data line, reducing parasitic capacitance coupling, and employs a data line selecting circuit that alternates the activation of transistors to minimize push down voltage, even in narrow-pitch layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor size is increased to achieve high-speed driving, then driving speed is improved, but parasitic capacitance increases leading to higher push down voltage and power consumption
Solution Approach 1:
The patent applies dimensionality change by arranging the gate electrode of the second transistor to overlap with the first data line instead of the second data line, utilizing the spatial dimension to reduce parasitic capacitance coupling while maintaining the transistor's driving function
Solution Approach 2:
The first data line serves as an intermediary element that prevents direct capacitance coupling between the gate electrode of the second transistor and the second data line, thereby reducing parasitic capacitance and push down voltage
2Area of stationary object
If pitch reduction is implemented, then device density is improved, but parasitic capacitance increases causing higher push down voltage
Solution Approach 1:
The patent utilizes spatial arrangement in another dimension by positioning the gate electrode to overlap with the adjacent first data line, creating a geometric configuration that reduces parasitic capacitance coupling even when pitch is reduced for higher device density
Solution Approach 2:
The patent introduces asymmetry in the layout configuration where the gate electrode of the second transistor overlaps with the first data line rather than its own second data line, creating an asymmetric arrangement that minimizes parasitic capacitance while maintaining compact pitch
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance and push down voltage, leading to lower power consumption and reduced heat generation, while maintaining display quality.
Implementation Method 1
The presence of the first data line prevents the capacitance coupling between the gate electrode of the second transistor and the second data line
Data Source
AI summary
An electrooptic device includes a scan line; data lines; a scan line driving circuit that selects the scan line; a data line driving circuit that supplies data signals to the data lines; a TFT that includes a gate electrode receiving gate signals for selecting the data line and has one end connected to the data line and the other end connected to the data line driving circuit; and a TFT that includes a gate electrode receiving gate signals for selecting the data line and has one end connected to the data line and the other end connected to the data line driving circuit. The gate electrode of the TFT overlaps the data line.