Electrophoretic Display Gate Drive Circuit With Lower Transistor Stress
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Solution Overview
Problem
The rate of transistor deterioration increases as the applied voltage increases in shift register circuits, particularly when the level of drive signals is elevated, as observed in existing shift register circuits like those described in JP 2020-135910 A.
Innovation Solution
A drive circuit configuration that includes a unit circuit with specific transistor connections and voltage differences, where the difference between the second and third voltages is smaller than the amplitude of the first voltage, reducing stress on transistors and thereby slowing deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the level of drive signal is increased, then the drive capability is improved, but the rate of transistor deterioration accelerates
Solution Approach 1:
The patent changes the voltage parameters applied to the transistors by introducing a DC offset voltage (Vdd) that is higher than the clock signal amplitude. This parameter change allows the transistor to operate with reduced stress despite maintaining high drive signal output levels, thereby resolving the contradiction between drive capability and transistor reliability
Solution Approach 2:
The patent applies a DC offset voltage beforehand to cushion the impact of high drive signal levels on the transistors. This pre-established voltage condition protects the transistors from excessive stress during operation, preventing accelerated deterioration while maintaining high drive capability
Data Source
AI summary
A unit circuit of a gate drive circuit includes a transistor to which a clock signal is applied, a transistor including a gate electrode to which a set signal is input, a source electrode to which a VDD signal is applied, and a drain electrode connected to a node, and a transistor including a gate electrode to which a reset signal is input, a sour electrode to which a VSS signal is applied, and a drain electrode connected to the node. A difference value between a voltage value of the VDD signal and a voltage value of the VSS signal is smaller than an amplitude of the clock signal.


