Electrophoretic Display Gate Voltage Staging for Artifact Control
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Solution Overview
Problem
Conventional electro-optic display driving techniques induce transient voltage artifacts during power up and power down processes, leading to optical defects and variations in display characteristics due to capacitive coupling between pixel electrodes and T-wires, which are not effectively mitigated by passive resistor-based solutions.
Innovation Solution
A method for driving electro-optic displays that involves applying a first stage voltage followed by a second stage voltage to the gate line, with specific magnitudes and durations to minimize voltage artifacts, using a controller to manage these voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single stage voltage is applied to the gate line during power up and power down, then the voltage transition is fast and simple, but transient voltage artifacts are induced on the electrophoretic layer causing optical defects
Solution Approach 1:
The voltage transition is divided into multiple stages instead of a single step change. The gate line voltage transitions through intermediate levels (e.g., first stage voltage, second stage voltage) before reaching the final gate low voltage, which segments the capacitive coupling effect and reduces transient artifacts on the electrophoretic layer.
Solution Approach 2:
A first stage voltage is applied before the final gate low voltage to prepare the system gradually. This preliminary voltage application allows the electrophoretic layer to adapt to changing electric fields in a controlled manner, preventing sudden voltage artifacts that would occur with direct single-stage transitions.
2Ease of manufacture
If passive resistor-based solutions are used to mitigate voltage artifacts, then the circuit implementation is simple, but the voltage artifacts are not effectively reduced
Solution Approach 1:
The invention changes the voltage parameter profile over time during power up and power down sequences. By controlling the temporal evolution of gate line voltage through multiple stages with specific durations, the system achieves effective artifact mitigation without requiring additional passive components like resistors, thus maintaining manufacturing simplicity while improving reliability.
3Manufacturing precision
If multi-stage voltage control is implemented, then voltage artifacts are reduced and display quality improves, but the control complexity increases
Solution Approach 1:
The voltage control follows a periodic sequence with defined stages and durations. The controller applies voltages in a repeating pattern (first stage voltage for first duration, second stage voltage for second duration, etc.), which provides systematic artifact reduction while maintaining manageable control logic through temporal structuring rather than spatial complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the amplitude of voltage artifacts on the electrophoretic layer, thereby maintaining consistent optical states and improving display quality by minimizing capacitive coupling effects.
Implementation Method 1
capacitive coupling between pixel electrodes and T-wires
Implementation Method 2
electrophoretic layer
Data Source
AI summary
An electro-optic display and driving method are disclosed. The electro-optic display includes a layer of electrophoretic material disposed between a common electrode and a backplane. The backplane includes an array of pixel electrodes, each coupled to a pixel transistor. A controller provides time-dependent voltages to the gate line, the source line, and the common electrode of each pixel transistor. The driving method includes applying a first stage voltage to the gate line. The first stage voltage has a first magnitude that is substantially half of a gate low voltage for placing the pixel transistor in a non-conducting state. The first stage voltage is maintained on the gate line for a first period of time. Then, a second stage voltage is applied to the gate line, where the second stage voltage has a second magnitude that is substantially the gate low voltage for placing the pixel transistor in the non-conducting state.