Electroplated Flip Chip Bumps for Low-Crosstalk Vertical Interconnects
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Solution Overview
Problem
Conventional fabrication processes for integrated circuit devices, especially those with heat and chemical-sensitive components like Josephson junction-based qubits, face challenges in maintaining component coherence due to exposure to heat and chemicals, leading to reduced coherence times and limitations in component density.
Innovation Solution
A method involving the formation of flip chip bumps on patterned wafers using an under bump metallization layer deposited at an angle, followed by electroplating to create flip chip bumps with a height of at least 15 μm, which allows for increased chip-to-chip separation and reduced capacitive coupling, thereby minimizing crosstalk and preserving sensitive components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for integrated circuit devices with heat and chemical-sensitive components, then manufacturing simplicity is maintained, but component coherence deteriorates due to exposure to heat and chemicals
Solution Approach 1:
The fabrication process is divided into distinct stages: forming under bump metallization layers, creating resist patterns, and electroplating flip chip bumps. This segmentation allows sensitive quantum processing unit components to remain on the wafer while only the interconnection structures are fabricated, minimizing exposure to harmful fabrication conditions.
Solution Approach 2:
Under bump metallization layers serve as intermediary structures between the patterned wafer and the flip chip bumps. These metallization layers are deposited and patterned first, creating protected intermediate structures that enable subsequent bump formation without directly exposing the sensitive quantum components to fabrication harshness.
2Quantity of substance
If component density is increased in three-dimensional integrated circuit devices, then circuit flexibility and density are improved, but manufacturing complexity increases
Solution Approach 1:
The patent extends interconnections into the vertical dimension by forming flip chip bumps that protrude from the wafer surface. This three-dimensional approach allows multiple layers of components to be interconnected, increasing component density without requiring proportional increases in planar fabrication complexity.
Solution Approach 2:
Under bump metallization layers are deposited and patterned in advance before the flip chip bumps are formed. This preliminary preparation of the metallization infrastructure simplifies the subsequent bump formation process and enables high-density interconnections to be established systematically.
3Object-affected harmful factors
If flip chip bumps with height of at least 15 μm are formed, then chip-to-chip separation is increased and capacitive coupling is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The mechanical deposition process is replaced with electroplating to form the flip chip bumps. Electroplating provides superior control over bump height and uniformity through electrical parameter control, enabling precise formation of bumps with heights of at least 15 μm while maintaining manufacturing feasibility.
Solution Approach 2:
The bump formation process utilizes electroplating parameters (current density, plating time, electrolyte composition) to precisely control the height and geometry of the flip chip bumps. By adjusting these parameters, the bump height can be controlled to be at least 15 μm, achieving the required chip-to-chip separation while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of high component density integrated circuit devices with improved coherence times for sensitive components, such as qubits, by reducing crosstalk and avoiding adverse effects from cavity modes, while allowing for increased component density and reduced capacitive coupling.
Implementation Method 1
The under bump metallization layer may be deposited by physical vapor deposition of the under bump metallization material
Implementation Method 2
physical vapor deposition of the under bump metallization material may be performed by electron beam evaporation
Implementation Method 3
Depositing the flip chip bumps by electroplating may include using the under bump metallization layer as a cathode such that flip chip bump material is deposited on sections of the under bump metallization layer that are exposed by the second openings in the second resist
Data Source
AI summary
The invention relates to a method for forming flip chip bumps using electroplating. The method allows the formation of flip chip bumps in a way that is compatible with already-formed sensitive electronic components, such as Josephson junctions, which may be used in quantum processing units. The invention also relates to a product and a flip chip package in which flip chip bumps are formed with the disclosed method.