Electroplated Metal Die Attach for Thermal Conductivity

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Solution Overview

Problem

Conventional die attach solutions using metal particle-filled polymers face significant thermal and electrical resistance issues, and solder die attach, while providing better performance, is expensive and limited to solderable surfaces, with processes that can induce temperature-induced stresses.

Innovation Solution

A multi-chip semiconductor package is developed using a plated metal die attach layer, such as copper, nickel, or their alloys, electroplated between the semiconductor die and the metal substrate, eliminating issues related to solder die attach processes and providing improved thermal and electrical conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal particle filled polymer die attach adhesive is used, then mechanical attachment is provided, but thermal and electrical resistance is significant

Engineering Contradiction:

Improvethermal conductivityVSAvoidthermal resistance

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent replaces expensive solder die attach with a cost-effective electroplated metal layer that provides superior thermal and electrical conductivity without the high costs associated with solder materials and reflow processing

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the fundamental parameter of die attach material from polymer-based adhesive to electroplated metal layer, transforming the thermal and electrical conductivity properties while maintaining mechanical attachment function

Inventive Principle:

Principle #35Parameter changes

2Reliability

If solder die attach is used, then good thermal and electrical conductivity is achieved, but cost increases and temperature-induced stresses occur

Engineering Contradiction:

Improveelectrical conductivityVSAvoidtemperature-induced stresses

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent replaces the thermal reflow process with electroplating, substituting a mechanical/thermal joining method with an electrochemical deposition process that occurs at lower temperatures, eliminating temperature-induced stresses on the semiconductor die

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The electroplated metal layer acts as an intermediary between the semiconductor die and substrate, providing both mechanical attachment and superior thermal/electrical conductivity pathways without requiring high-temperature processing

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If solder die attach is used, then back side electrical contact is provided, but the process is limited to solderable surfaces

Engineering Contradiction:

Improvesurface compatibilityVSAvoidprocess limitations

Core Design Contradiction:

Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The electroplating process provides universal applicability to various die surface types and materials, making the die attach method versatile and not limited to solderable surfaces, thereby enhancing adaptability across different semiconductor devices

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution offers a high thermal conductivity and low electrical resistance die attach arrangement that avoids temperature-induced stresses, enhancing the performance of semiconductor devices with improved reliability and cost-effectiveness.

Implementation Method 1

a plated metal die attach layer, such as copper, nickel, or their alloys, electroplated between the semiconductor die and the metal substrate

Methodology Applied

Scientific EffectElectroplating: Electroplating

Implementation Method 2

providing a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures... high thermal conductivity die attach arrangement

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 3

providing a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures... low electrical resistance

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10957635B2Multi-chip package with high thermal conductivity die attach

Publication Date: 2021.03.23 TEXAS INSTRUMENTS INC

AI summary

A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.