Electroplated Pillar Arrays for Uniform Height Across Density Variations
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Solution Overview
Problem
Conventional electrochemical plating processes for forming pillars in semiconductor die assemblies result in non-uniform pillar heights due to varying lateral densities, leading to unreliable electrical and thermal connections between stacked dies.
Innovation Solution
The use of pillars with different target widths and the strategic placement of dummy pillars to offset the effects of differing lateral densities on metal deposition rates during electrochemical plating, ensuring uniform pillar heights and reliable interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional electrochemical plating is used to form pillars, then the plating process is simple and cost-effective, but the pillar heights become non-uniform due to varying lateral densities
Solution Approach 1:
The patent applies local quality by introducing dummy pillars specifically in regions with low lateral density. These dummy pillars are strategically placed to locally increase the metal ion concentration in sparse regions, thereby equalizing the plating rate across different regions of the wafer without modifying the overall plating process or affecting high-density regions.
Solution Approach 2:
The patent employs preliminary anti-action by pre-compensating for the expected non-uniformity in pillar heights through the strategic placement of dummy pillars before plating begins. The dummy pillars are positioned in advance to counteract the anticipated depletion of metal ions in low-density regions, thereby preventing height variations rather than correcting them after plating.
2Manufacturing precision
If pillars are formed with uniform lateral density, then metal deposition is uniform, but the design flexibility for different functional regions is limited
Solution Approach 1:
The patent enables different functional regions to have different pillar densities while maintaining uniform plating by applying local quality through dummy pillars. High-density regions maintain their original pillar patterns for specific functions, while low-density regions receive dummy pillars to compensate for plating non-uniformity, thus preserving design flexibility across the wafer.
Solution Approach 2:
The patent segments the wafer into different functional regions with different pillar density requirements. Each region is independently optimized: signal pillars in high-density regions for electrical connectivity, thermal pillars in low-density regions for heat dissipation, and dummy pillars strategically placed to ensure uniform plating across all regions without compromising functional performance.
3Measurement precision
If photoresist masking is used to define pillar locations, then precise pillar placement is achieved, but the process complexity and material usage increase
Solution Approach 1:
The patent merges the formation of dummy pillars with the existing photoresist patterning process. The same photoresist layers and patterning steps used to define functional pillars are also used to define dummy pillar locations, thereby achieving precise pillar placement without adding separate masking processes or increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces height variations among pillars, enhancing the reliability of electrical and thermal connections between dies, thereby improving the overall performance and reducing scrap rates of semiconductor packages.
Implementation Method 1
metal is electrochemically plated onto the unmasked portion of the die surface
Data Source
AI summary
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.