Electroplated Posts With Planarizing Dielectric Structures

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Solution Overview

Problem

Conventional flip chip bonding techniques using electroplated copper posts suffer from non-planar surfaces leading to voids in solder joints, resulting in poor electrical contact and reliability issues, and varying post heights due to different electroplating rates, making uniform solder joint formation difficult.

Innovation Solution

The use of planarizing dielectric structures on bond pads to create electroplated metal posts with substantially planar surfaces and uniform heights, which also act as a stress buffer to reduce delamination and improve reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electroplated copper posts are formed on bond pads, then electrical connections are enabled, but the surface becomes non-planar causing voids in solder joints

Engineering Contradiction:
Improvesolder joint qualityVSAvoidsurface planarity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A planarizing dielectric layer is introduced as an intermediary between the electroplated copper post and the solder joint. This dielectric layer has a planar top surface that compensates for the non-planar post surface, ensuring uniform solder joint formation without voids while maintaining electrical connectivity through the underlying post structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If electroplating is performed on posts of different areas, then current carrying capability is optimized, but posts grow at different rates resulting in non-uniform heights

Engineering Contradiction:
Improvecurrent carrying capabilityVSAvoidpost height uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The planarizing dielectric layer is selectively applied to different bond pad regions based on their specific requirements. Larger area posts receive thinner dielectric coverage to maintain current carrying capability, while smaller posts receive thicker coverage to achieve uniform top surfaces, allowing each region to have optimized local properties while achieving global uniformity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures consistent, high-quality solder joints with improved electrical contact and reliability by maintaining planarity and uniformity of electroplated posts, while reducing stress-related failures.

Implementation Method 1

The planarizing dielectric structues may also act as a stress buffer layer and may relieve stress between the electroplated post and the bond pad

Methodology Applied
Scientific EffectStress buffering: Elasticity

Implementation Method 2

metal posts (usually copper) are first electroplated on top of the integrated circuit chip bond pads

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS8476760B2Electroplated posts with reduced topography and stress
Publication Date: 2013.07.02 TEXAS INSTRUMENTS INC
  • US8476760B2 patent drawing
  • US8476760B2 patent drawing
  • US8476760B2 patent drawing

AI summary

Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.