Electroplated Via Structure for Back-End Space Optimization

The patent extracts the via formation process from the traditional hole-etching method and replaces it with a built-up structure. Instead of removing material to create vias, the invention builds conductive structures (traces and columns) directly on the insulating layer surface, eliminating the need for hole formation and associated space consumption for pads and isolation.

The patent transitions from a planar via structure (holes through insulating layers) to a three-dimensional built-up structure (traces and columns on the surface). This dimensional change allows electrical connectivity to be achieved without consuming lateral space, as the conductive paths extend vertically rather than requiring lateral hole formation.

The patent removes the need for isolation structures and pads that traditionally surround etched vias. By building conductive structures on the surface rather than etching holes, the invention eliminates the requirement for additional isolation material and pad structures, simplifying the overall device architecture.

The patent merges the via formation process with the existing trace patterning process. The same electroplating techniques used to form traces are also used to form columns, integrating two functions into a unified process flow and reducing the number of separate manufacturing steps required.

The patent moves via formation from a lateral process (etching holes through the insulating layer) to a vertical process (building columns on the surface). This dimensional shift preserves lateral space in the back-end layers, allowing more room for other circuit elements while maintaining via formation capability.

The patent performs trace and column formation before final insulation layer application. By building the conductive structures first and then adding insulation around them, the process maximizes space utilization and allows subsequent layers to be optimized without being constrained by pre-formed via holes.