Element Chip Manufacturing Method for Plasma Dicing Bump Protection

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Solution Overview

Problem

The existing plasma dicing method for singulating substrates with bumps exposes the metal bumps to plasma, leading to metal scattering, unstable plasma generation, contamination, and degradation of device characteristics, reducing the reliability and productivity of element chip production.

Innovation Solution

A method involving a protection tape with an adhesive layer to embed and protect the bump, allowing plasma etching from the opposite surface, thereby preventing metal exposure and contamination, and using a thinning process to reduce substrate warping and internal stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If plasma dicing is performed on a substrate with exposed bumps, then the singulation process can be completed, but metal scattering occurs leading to unstable plasma generation and contamination

Engineering Contradiction:
Improvesingulation process completionVSAvoidplasma generation stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A resist mask is introduced as an intermediary substance between the plasma and the metal bump. The resist mask absorbs the harmful interaction by being etched instead of the metal bump, preventing metal scattering while allowing the plasma dicing process to proceed normally. This mediator protects the metal bump from direct plasma exposure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The resist mask is applied in advance to the substrate surface before plasma dicing begins. This preliminary action creates a protective barrier that prevents the anticipated harmful effect of plasma-metal interaction. The resist mask is specifically patterned to cover the bump areas while exposing the dicing lines, preemptively blocking potential metal scattering.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If a thick resist mask is formed to cover the bump, then plasma exposure of the bump is prevented, but the time required for plasma ashing increases reducing productivity

Engineering Contradiction:
Improvebump protection from plasmaVSAvoidplasma ashing time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The resist mask is applied with spatial variation in thickness and coverage. Rather than uniformly covering the entire substrate, the resist mask is selectively applied only where needed - specifically covering the metal bump areas while leaving the dicing line areas exposed. This local differentiation allows adequate bump protection with minimal resist material, thus reducing ashing time.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of applying a uniformly thick resist mask across the entire substrate, the invention uses partial coverage with optimized thickness only in the critical bump regions. The resist mask thickness is carefully controlled to be sufficient for protection where needed (at the bump locations) while minimizing the total amount of resist material, thereby reducing the plasma ashing time required.

Inventive Principle:
Principle #16Partial or excessive action

3Strength

If the substrate is plasma diced from the circuit layer surface, then damage to the bump is prevented, but the bump is exposed to plasma causing metal scattering

Engineering Contradiction:
Improvebump mechanical protectionVSAvoidmetal scattering
Core Design Contradiction:
StrengthVSObject-generated harmful factors

Solution Approach 1:

The resist mask serves as an intermediary that changes the etching sequence. By applying the resist mask first, the plasma etching selectively removes the resist material at the dicing lines while the metal bump remains protected underneath the resist coverage. This intermediary layer enables the circuit layer to be etched without direct plasma-bump contact, preventing metal scattering while maintaining mechanical protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The resist mask is applied in advance to the substrate before plasma dicing begins. This preliminary action establishes a protective pattern that guides the subsequent plasma etching process. The pre-applied resist mask ensures that when plasma contact occurs, only the resist material is removed at the dicing lines while the metal bump remains shielded, preventing metal scattering before it can occur.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach stabilizes plasma generation, enhances etching reproducibility, improves the smoothness and flexural strength of element chips, reduces etching residue and contamination, and increases production yield while maintaining device characteristics and reliability.

Implementation Method 1

adhering a protection tape having an adhesive layer to the first surface and embedding at least a head top part of the bump into the adhesive layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

a method (plasma dicing) for plasma etching the dividing regions to a depth which extends from one surface of the substrate to the other surface

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS10049933B2Element chip manufacturing method
Publication Date: 2018.08.14 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US10049933B2 patent drawing
  • US10049933B2 patent drawing
  • US10049933B2 patent drawing

AI summary

An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.